Trying to integrate verilog file into vhdl project

Altera_Forum · ‎01-24-2011

Hi

I'm sure this question has been asked before but I can't seem to find an answer to it.

I am trying to use a verilog file in a vhdl project like this:

u1 : entity work.sdram port map(

CLOCK_50=>systemClk,

SW=>input,

LEDG=>sdramLedG,

LEDR=>sdramLedR

);

However when I try to compile it gives

Error (10481): VHDL Use Clause error at sdram_driver_test.vhd(25): design library "work" does not contain primary unit "sdram"

Trying without the work doesn't work either.

Any ideas?

Altera_Forum · ‎01-24-2011

add a VHDL component declaration for sdram. i don't think direct instantiation will work mixed language without a component declaration

Altera_Forum · ‎01-24-2011

You have to treat the verilog like a black box. so you will need a component declaration else the VHDL has no knowledge of the existance of the Verilog, and hence throws the error. This way you can instantial verilog or AHDL entities from VHDL.