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Altera_Forum
Honored Contributor I
1,322 Views

How to export signals from a UART (TX,RX) in verilog

Hi,  

 

I was hoping somebody could tell me how to correctly export signals from a UART in a NIOS II.  

 

I created a NIOS using QSYS with switches, lights and a UART. I have exported all of these block so that I can assign them pins.  

 

 

My top level verilog code where the NIOS is instantiated is located. 

 

My question is - how to I export the signals for the UART (TX, RX) which has both input and output? 

 

My code below, is giving an error on .uart_export(TX,RX),, as using a comma is incorrect.  

 

I need to do this so that I can assign the pins to GPIO on development board.  

 

Thanks 

 

// Implements a simple Nios II system for the DE-series board. // Inputs: SW7-0 are parallel port inputs to the Nios II system // CLOCK_50 is the system clock // KEY0 is the active-low system reset // Outputs: LEDR7-0 are parallel port outputs from the Nios II system module lights (CLOCK_50, SW, KEY, LEDR, TX, RX); input CLOCK_50; input SW; input KEY; output LEDR; input RX; output TX; // Instantiate the Nios II system module generated by the Qsys tool: nios_system NiosII ( .clk_clk(CLOCK_50), .reset_reset_n(KEY), .switches_export(SW), .uart_export(TX,RX), .leds_export(LEDR)); endmodule
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4 Replies
Altera_Forum
Honored Contributor I
88 Views

It's very difficult to see your attached image, but uart_export is two separate signals. An interface in Qsys, including an exported interface, can consist of more than one signal. Interfaces are essentially signal bundles. From the Generate menu in Qsys, look at the instantiation template. This will tell you how to instantiate the system in the top level.

Altera_Forum
Honored Contributor I
88 Views

Altera_Forum
Honored Contributor I
88 Views

Like I said, uart_export is multiple signals. Use the instantiation template to instantiate it correctly.

Altera_Forum
Honored Contributor I
88 Views

Please reupload your attached image.

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