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Altera_Forum
Honored Contributor I
2,238 Views

How to find problem in design after compiliation / fitter failure

Hello everyone. 

 

I have created a project that according to the HTML report has the following estimates: 

 

 

 

[TH="class: res-title, align: left"]Kernel Name[/TH] 

[TH="class: res-val, align: left"]ALUTs[/TH] 

[TH="class: res-val, align: left"]FFs[/TH] 

[TH="class: res-val, align: left"]RAMs[/TH] 

[TH="class: res-val, align: left"]DSPs[/TH] 

 

 

Total 

61485 (56%) 

72984 (33%) 

322 (63%) 

94 (84%) 

 

 

Available 

109572 

219144 

514 

112 

 

 

 

In the file top.fit.rpt I can see the following summary after compilation: 

 

; Fitter Summary ; +---------------------------------+-------------------------------------------------+ ; Fitter Status ; Failed - Wed Apr 25 23:51:32 2018 ; ; Quartus Prime Version ; 17.1.0 Build 590 10/25/2017 SJ Standard Edition ; ; Revision Name ; top ; ; Top-level Entity Name ; top ; ; Family ; Cyclone V ; ; Device ; 5CSEMA5F31C6 ; ; Timing Models ; Final ; ; Logic utilization (in ALMs) ; 32,070 / 32,070 ( 100 % ) ; ; Total registers ; 65218 ; ; Total pins ; 115 / 457 ( 25 % ) ; ; Total virtual pins ; 0 ; ; Total block memory bits ; 1,389,980 / 4,065,280 ( 34 % ) ; ; Total RAM Blocks ; 0 / 397 ( 0 % ) ; ; Total DSP Blocks ; 87 / 87 ( 100 % ) ; ; Total HSSI RX PCSs ; 0 ; ; Total HSSI PMA RX Deserializers ; 0 ; ; Total HSSI TX PCSs ; 0 ; ; Total HSSI PMA TX Serializers ; 0 ; ; Total PLLs ; 2 / 6 ( 33 % ) ; ; Total DLLs ; 1 / 4 ( 25 % ) ; +---------------------------------+-------------------------------------------------+ 

 

However, the process fails with the following message in the same file: 

 

Error (170012): Fitter requires 3213 LABs to implement the design, but the device contains only 3207 LABs 

 

I can't find the reason for this and in contrast to the HTML report there is no link to which lines of the source code are causing what resource usage. Is there any way to get a more accurate HTML report based on the actual compilation to find the reason for the increased resource usage? It seems there is quite a discrepancy between the estimate and the actual usage so I wonder how this can be traced / understood and fixed in the code. Any ideas are much appreciated. 

 

Board: Cyclone V, 5CSXFC6D6F31C8ES, de1soc:de1soc_sharedonly
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7 Replies
Altera_Forum
Honored Contributor I
213 Views

As a first, quite obvious answer, the estimation has been done for a different device. The final implementation is running short of DSP blocks, apparently consumes many ALMs to replace it.

Altera_Forum
Honored Contributor I
213 Views

Thanks for your reply. I doubt this is the case because the report is being created at the same time with the full flow compilation for the device (Terasic DE1-SoC). This is the device line from the report: 

Target Family, Device, Board: Cyclone V, 5CSXFC6D6F31C8ES, de1soc:de1soc_sharedonly 

This is the device info from the top.fit.rpt file: 

; Family ; Cyclone V ; ; Device ; 5CSEMA5F31C6 ; 

For me they look like they are for the same device. Are they not? 

 

edit: Taking a closer look at the device codes it seems that 5CSXFC6D6F31C8ES does not match the DE1-SoC board. How can this be? Looking at the Cyclone V product table this would be a Cyclone V SX SoC instead of a Cyclone V SE SoC. Any ideas? 

 

It makes sense the DSPs are the bottleneck, I will look into it and see if I can somehow reduce the DSP usage further. If you have any further ideas regarding how to make the HTML report more accurate (after the full flow compilation i mean) it would be awesome! Thanks again.
Altera_Forum
Honored Contributor I
213 Views

Isn't it possible to make the report for the same device that is used in the compilation?

Altera_Forum
Honored Contributor I
213 Views

I wish it was, but how? I am not doing anything to change the board myself, so how can I make it for the same device? This is the command I use for compilation: 

aoc -o t_device -v -I/x/inc -I/x/bin2 -I/y/intelFPGA/17.1/hld/include/kernel_headers -board=de1soc_sharedonly -profile -high-effort -fp-relaxed -fpc -seed=3 /x/device/device.cl 

I suspect the Terasic board support package might be incomplete because the board_spec.xml file does not contain a line containing 5CSEMA5F31C6, only this one: <device device_model="5csxfc6d6f31c8es_dm.xml">. 

 

File board_spec.xml: 

<?xml version="1.0"?> <board version="14.1" name="de1soc_sharedonly"> <compile project="top" revision="top" qsys_file="system.qsys" generic_kernel="0"> <generate cmd="ip-generate --component-file=system.qsys --file-set=QUARTUS_SYNTH --output-directory=system/synthesis --report-file=qip:system/synthesis/system.qip --jvm-max-heap-size=3G"/> <synthesize cmd="quartus_sh --flow compile top -c top"/> <auto_migrate platform_type="c5soc" > <include fixes=""/> <exclude fixes=""/> </auto_migrate> </compile> <device device_model="5csxfc6d6f31c8es_dm.xml"> <used_resources> <alms num="1080"/><!-- ALMs used for LUT logic + ALMs used for LUT logic and registers--> <ffs num="1908"/> <dsps num="0"/> <rams num="20"/> </used_resources> </device> <!-- One DDR3-800 DIMM, 256-bit data --> <global_mem max_bandwidth="6400"> <interface name="acl_iface" port="kernel_mem0" type="slave" width="256" maxburst="16" latency="240" address="0x00000000" size="0x40000000"/> </global_mem> <host> <kernel_config start="0x00000000" size="0x0100000"/> </host> <interfaces> <interface name="acl_iface" port="kernel_cra" type="master" width="64" misc="0"/> <interface name="acl_iface" port="kernel_irq" type="irq" width="1"/> <kernel_clk_reset clk="acl_iface.kernel_clk" clk2x="acl_iface.kernel_clk2x" reset="acl_iface.kernel_reset"/> </interfaces> </board>
Altera_Forum
Honored Contributor I
213 Views

Hmm, this seems very strange. Many people new to OpenCL on FPGAs use Terasic's low-cost Cyclone boards, someone should have seen this by now. I recommend bringing up the matter with Terasic's support.

Altera_Forum
Honored Contributor I
213 Views

Thanks, I will contact them and report back. If any ideas come up meanwhile, let me know.

Altera_Forum
Honored Contributor I
213 Views

It turns out that Terasic does not use the board_spec.xml file for generating their BSP, hence the wrong values. They instead modify the .dts file directly to generate the device tree / .dtb file. Unfortunately I could not get a reply on how to correctly set the parameters for the board_spec.xml file to make the HTML report more accurate. I am now using these values: 

 

File hld/share/models/dm/5csema5f31c6_dm.xml: 

<!-- Device model for: 5CSEMA5F31C6 --> <device_model version="0.9" target_model="cyclonev_tm.xml"> <fmax expected="200" min="100" high="175"/> <resources> <alms num="32070"/> <ffs num="128280"/> <dsps num="87"/><!-- variable precision DSP blocks --> <rams num="3970"/><!-- M10Ks --> </resources> </device_model> 

For the number of FFs I guessed it should be four times the number of ALMs. The values for fmax-{expected, min, high} are from the reference kit and I have no idea if these are close-enough values... The resource estimate is much closer to reality now. 

 

To use the file above, I had to replace  

<device device_model="5csxfc6d6f31c8es_dm.xml"> 

with 

<device device_model="5csema5f31c6_dm.xml"> 

in the board_spec.xml file.
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