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How to fix warning when using parameters in verilog file in component editor.

HTork
Beginner
297 Views

Hello! I doing a design for an old system using Cyclone II device and developing with quartus 11 and sopc builder.

 

I have a verliog file <design.v> that use with component editor to create an IP. In this verilog file I use parameters to set some register values.

 

When compiling the design I get the following typw of warning on these parameters:

 

Warning (10230): Verilog HDL assignment warning at <design>.v(<line number>): truncated value with size xx to match size of target (yy)

 

If I use localparam instead, I get no warnings. Thus, the problem with the warnings are probably related to the HDL parameters tab in component editor.

In HDL parameters tab I can choose between several types for my parameters: string, integer, boolean, std_logic, logic vector, natural, or positiv. If I try to change the parameter type, the component editor hangs, and I have to close it. Also there is no description of what these types are..

 

I would not like to change my paramters to localparam since I would like to be able to oveeride them when simulating the system.

So, how do i fix the problem with these warnings.

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1 Reply
AnandRaj_S_Intel
Employee
127 Views

Hi Hans,

 

Share your Verilog file.

 

For descriptions on the parameter type refer to page 155 on below link

https://www.intel.co.jp/content/dam/altera-www/global/ja_JP/pdfs/literature/hb/qts/qsys_intro.pdf

 

Regards

Anand

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