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Altera_Forum
Honored Contributor I
1,281 Views

Problem with the error Top partition does not contain any logic

Hellow, my problem is that my code compile until 50%, but this show me the error Top partition does not contain any logic, this code is my test bench of other code with 2 inputs with the specify bits for each one and the output of 4 bits. I am trying with this code a clock for each bit with diferent period and iam trying to prove some inputs. 

 

`timescale 1ns / 1ns  

//clock generation using initial and always statements 

 

 

module TodoUnido_V (); 

reg [9:0]A; 

reg [5:0]B; 

wire [5:0]Dia; 

 

 

TodoUnido  

DUT (A[9:0],B[5:0],Dia[4:0]); 

 

 

initial  

begin 

A[9] = 1'b0 ; 

# 5 

A[9] =~ A[9]; 

 

A[8] = 1'b0 ; 

//#10 

//A[8] =~ A[8]; 

 

 

A[7] = 1'b0 ; 

# 5 

A[7] =~ A[7]; 

 

A[6] = 1'b0 ; 

//#5 

//A[6] =~ A[6]; 

 

A[5] = 1'b0 ; 

# 5 

A[5] =~ A[5]; 

 

A[4] = 1'b0 ; 

//#5 

//A[4] =~ A[4]; 

 

A[3] = 1'b0 ; 

# 5 

A[3] =~ A[3]; 

 

A[2] = 1'b0 ; 

//#5 

//A[9] =~ A[9]; 

 

A[1] = 1'b0 ; 

# 5 

A[1] =~ A[1]; 

 

A[0] = 1'b0 ; 

//# 5 

//A[9] =~ A[9]; 

 

 

 

B[5] = 1'b0 ; 

# 160 

B[5] =~ B[5]; 

 

B[4] = 1'b0 ; 

//# 160 

//P[5] =~ P[5]; 

 

B[3] = 1'b0 ; 

# 160 

B[3] =~ B[3]; 

 

B[2] = 1'b0 ; 

# 160 

B[5] =~ B[5]; 

 

B[1] = 1'b0 ; 

//#160 

//P[1] =~ P[1]; 

 

B[0] = 1'b0 ; 

//# 160 

//P[0] =~ P[0]; 

 

 

end 

 

 

 

//determine length of simulation 

initial 

# 400 $finish; 

 

 

endmodule
0 Kudos
2 Replies
Altera_Forum
Honored Contributor I
215 Views

This design does no contain any logic, because it appears to be test code. 

What is the DUT? have you tried synthesising that on its own?
Udith
Beginner
215 Views

Try this.. It worked for me...

First make the Module code as the top level entity (not the test-bench) then compile...