How to heat FPGA at max power consumption?

[Henry]

I am new to Intel FPGA.

Is there any code or tutorial about stress FPGA at max power consumption?

I try to use a lot of register, however compiler seems will simplify my design, so that I can't get a higher power consumption design.

here is an example code from Xilinx I use:

-------------------------------

logic sig100tr =0;

always_ff@(posedge clk500) begin

if (rst) begin

sig100tr <=0;

end else begin

sig100tr <=~sig100tr; // a signal with 100% toggle rate at 500MHz

end

end

local param N3=50000;

(*DONT_TOUCH="TRUE"*)

FDCE#( .INIT( 1'b0 ) // Initial value of register (1'b0 or 1'b1) )

FDCE_1 [N3:1] (

.Q( ), // 1-bit Data output

.C( clk500 ), // 1-bit Clock input

.CE( 1'b1 ), // 1-bit Clock enable input

.CLR( 1'b0 ), // 1-bit Asynchronous clear input

.D( sig100tr ) // 1-bit Data input

);

[AndyN]

Try this:

(* noprune *) logic [N3-1:0] toggles = '0;   always_ff @(posedge clk500) toggles <= ~toggles;

I've found the noprune directive to be more reliable than don't_touch for some reason...

Andy

[Henry]

thanks,

I use about 1M register, the power consumption is about 80W much lower than stratix 10 spec 170W.

Have any idea to increase power consumption?

increase more register and reverse it is the best solution?

localparam N = 1000000;

(* noprune *) reg [N:0] reg = 0;

always @ (posedge clk_600)

begin

reg <= ~reg;

end

[AndyN]

Keep in mind that the test as you are currently doing it is only toggling registers - there's presumably no use of DSP or transceivers, both of which are big power draws when in use. It's all a question of what you are actually trying to achieve with this test...