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Altera_Forum
Honored Contributor I
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How to instantiate multiple components with variable number of ports in vhdl?

I want to instantiate several times a couple of components using a for generate syntax, these components have a variable number of ports and I don't have an idea of how assing these variable size ports to signals. 

I'm using a package with this declaration : 

 

PACKAGE Arrays_package IS 

type Generic_ARRAY_type is array(integer range <>) of std_logic_vector; 

END Arrays_package; 

 

the couple of components are pre_pre_buffer_conv and pre_buffer_conv and the code is presented below. How I can to declare the signal xdataout_preprebuffer

 

the errors thrown by analysis & elaboration stage were these 

 

Error (10381): VHDL Type Mismatch error at Naive_RNC_problem.vhd(235): indexed name returns a value whose type does not match "Generic_ARRAY_type", the type of the target expression 

Error: Quartus Prime Analysis & Elaboration was unsuccessful. 1 error, 0 warnings 

 

 

 

I believe that the signal xdataout_preprebuffer have to be declared as 2d array signal, but I don't know how to accomplish that. 

thanks, and sorry for my english
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Altera_Forum
Honored Contributor I
185 Views

Hi, 

 

--- Quote Start ---  

the couple of components are Pre_pre_buffer_conv and Pre_buffer_conv and the code is presented below. How I can to declare the signal xdataout_preprebuffer?  

--- Quote End ---  

 

Can you check with, 

Replace xdataout_preprebuffer(i) with xdataout_preprebuffer 

No need to use ….(i) in other places as well in entire code. 

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance. 

 

Best Regards 

Vikas Jathar  

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
185 Views

The problem arrises because the pre_pre_buffer_conv entity requires a connection that is a Generic_ARRAY_type, but it is a different size to the input data type. The initial problem is that xdataout_preprebuffer(i) is a single std_logic_vector that is no_bits wide.  

 

But the connection requires a Generic_ARRAY_type that is no_col_filt entries of std_logic_vector(no_col_fil*no_bits-1 downto 0). So this array dimensions do not map to the input at all. 

You need to somehow create a teporary signal inside the entity that will re-map the input array to the required size. It also should not be in a generate loop as it currently is.
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