How to interface between user logic and Qsys(Platform) in AVMM PCIe ref-design?

[MinzhiWang]

Hello Guys,

I'm studying Avalon-MM DMA PCIe referent design. Our target device is 10cx220yf780e5g.  I can find the ref-design from Intel website and correspoinding an doc, an690.

But the ref-design is just for reference. avmm all implemented inside Qsys, so i need to combine with my own logic, as following image.

For me, above green square frame is as black box. User how to realize the communication channel between their own logic and that on-chip memeory inside Qsys?

[Wincent_Altera]

Hi ,

Thanks for reaching, I never implement the same as you.

But I can lay down some of suggestion based on my experience, how that give you some idea to move forward.

1. Ensure that your custom logic has Avalon-MM interfaces that can communicate with other components in the Qsys system.
2. Typically, you will need to define Avalon-MM master or slave interfaces depending on whether your logic will be reading from or writing to the on-chip memory.
3. Add your custom logic as a new component. You can do this by creating a new component in Platform Designer and specifying the Avalon-MM interfaces.
4. Connect the Avalon-MM interfaces of your custom logic to the appropriate interfaces in the Qsys system. For example, if your custom logic needs to access on-chip memory, connect it to the memory-mapped slave interface of the on-chip memory.

Hope that able to help you to move forward. But we do advise to follow the example design as it is well tested.

Regards,

Wincent

[MinzhiWang]

Hi Wincent,

Thanks for you reply.

In our application, the data are stored in an FIFO. So the data transfer between user logic and Qsys lay on between FIFO and the On-chip memory in Qsys.

As you said, we can't connect FIFO interface to that On-chip memory directly. We have to design one extra AVMM master for our FIFO?

Could you provide some simple tutorial papers for us to learn?

Thanks

[FvM]

Hi,
you can start with the example project and modify the module that connects on-chip RAM as AVMM slave, e.g. xxx_integrated_onchip_memory. You'll use one port for the AVMM and one for the user logic interface. clk, address data and control signals of the user interface have to be exported as conduit which make them appear on the top level of the Qsys design.

[MinzhiWang]

Hi FvM,

Thanks for you reply.

I noticed that the on-chip RAM is connected to several master. Now one more master implemented with me will be connected to it. So how to avoid the confilict among multiple masters to access single on-chip RAM? And how user logic to know when the on-chip RAM is ready for it to access this on-chip ram?

Thanks

[Wincent_Altera]

Hi Minzhi,

You can try to check the Arbitration settings, click on the interconnect that connect the master to ram
properties pane, you can configure the arbitration scheme (e.g., round-robin, priority-based).
Detail, you may refer to 4.7. Avalon® -ST Round Robin Scheduler

The Avalon® -ST Round Robin Scheduler core controls the read operations from a multi-channel Avalon® -ST component that buffers data by channels. The Request Interface is an Avalon® -MM write master interface that requests data from a specific channel. The Avalon® -ST Round Robin Scheduler cycles through the channels it supports and schedules data to be read.

Hope that can help you to move forward.

Regards,

Wincent

[Wincent_Altera]

Hi,

I wish to follow up with you about this case.

Do you have any further questions on this matter ?

​​​​​​​Else I would like to have your permission to close this forum ticket. Nevertheless, you can still response to the forum and I will be available to assist you.

Regards,

Wincent_Intel

p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.

[MinzhiWang]

Hi,

Yes, you can close it. I think I need more practice for Platform operation.

Thanks

[Wincent_Altera]

Hi Minzhi,

Thanks for your confirmation, I will transitioned this to community support

If you have a new question, feel free to open a new thread to get support from Altera.

If your support experience falls below a 9 out of 10, I kindly request the opportunity to rectify it before concluding our interaction. If the issue cannot be resolved, please inform me via this forum page of the cause so that I can learn from it and strive to enhance the quality of future service experiences. 

Regards,

Wincent

p/s: If any answer from the community or Intel Support is helpful, please feel free to give the best answer or rate 9/10 survey.