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How to interface my verilog code with FFT ip core

Altera_Forum
Honored Contributor II
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I'm working on an application that involves the FPGA to take in an analog signal through its onboard ADC and perform the FFT using the altera ip core. 

 

So far, my understanding is the ip core generates a verilog module for just the FFT and I will have to instance it in my own code. First question: is that piece of understanding correct? 

 

The verilog file that the core generated looked like: 

 

 

// Generated using ACDS version 15.0 153 

 

 

`timescale 1 ps / 1 ps 

module myFFT512 ( 

input wire clk, // clk.clk 

input wire reset_n, // rst.reset_n 

input wire sink_valid, // sink.sink_valid 

output wire sink_ready, // .sink_ready 

input wire [1:0] sink_error, // .sink_error 

input wire sink_sop, // .sink_sop 

input wire sink_eop, // .sink_eop 

input wire [31:0] sink_real, // .sink_real 

input wire [31:0] sink_imag, // .sink_imag 

input wire [9:0] fftpts_in, // .fftpts_in 

output wire source_valid, // source.source_valid 

input wire source_ready, // .source_ready 

output wire [1:0] source_error, // .source_error 

output wire source_sop, // .source_sop 

output wire source_eop, // .source_eop 

output wire [31:0] source_real, // .source_real 

output wire [31:0] source_imag, // .source_imag 

output wire [9:0] fftpts_out // .fftpts_out 

 ); 

 

 

myFFT512_fft_ii_0 fft_ii_0 ( 

.clk (clk), // clk.clk 

.reset_n (reset_n), // rst.reset_n 

.sink_valid (sink_valid), // sink.sink_valid 

.sink_ready (sink_ready), // .sink_ready 

.sink_error (sink_error), // .sink_error 

.sink_sop (sink_sop), // .sink_sop 

.sink_eop (sink_eop), // .sink_eop 

.sink_real (sink_real), // .sink_real 

.sink_imag (sink_imag), // .sink_imag 

.fftpts_in (fftpts_in), // .fftpts_in 

.source_valid (source_valid), // source.source_valid 

.source_ready (source_ready), // .source_ready 

.source_error (source_error), // .source_error 

.source_sop (source_sop), // .source_sop 

.source_eop (source_eop), // .source_eop 

.source_real (source_real), // .source_real 

.source_imag (source_imag), // .source_imag 

.fftpts_out (fftpts_out) // .fftpts_out 

 ); 

 

 

endmodule 

 

How do I instance that module in my own code? I do not recognize the syntax of ".fftpts_out (fftpts_out) " at all. Where can I read up on this?
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Altera_Forum
Honored Contributor II
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Instantiate the code by copy and pasting the second half of generated file (that you've included above) in your higher level module. Substitute, as necessary, the signal names in the parenthesis for signals available in your higher level module to make connections to/from the FFT module instance. 'myFFT512_fft_ii_0' will be the instance name. 

 

Cheers, 

Alex
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