- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello,
I have used two clocks in my design.Both clocks are generated from same PLL.Clock frequency of one clock is 50MHz and frequency of other is 55MHz.I am transferring data between 50MHz and 55MHz. I have taken care of CDC in my design.My question is (1) Can I provide false path between two clocks? In one of the post, I read that PLL output clocks are synchronized with PLL input and synchronize with each other as well. (2) How 50MHz and 55MHz clocks can be synchronous? Does timequest look for the repetitive pattern and based on that it decide whether clock is synchronous or asynchronous? (3) I have taken care for the naming convention while transferring data from one clock domain to another clock domain.So based on that I can provide false path between nodes. Regards, KrupeshLink Copied
5 Replies
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
--- Quote Start --- Hello, I have used two clocks in my design.Both clocks are generated from same PLL.Clock frequency of one clock is 50MHz and frequency of other is 55MHz.I am transferring data between 50MHz and 55MHz. I have taken care of CDC in my design.My question is (1) Can I provide false path between two clocks? In one of the post, I read that PLL output clocks are synchronized with PLL input and synchronize with each other as well. (2) How 50MHz and 55MHz clocks can be synchronous? Does timequest look for the repetitive pattern and based on that it decide whether clock is synchronous or asynchronous? (3) I have taken care for the naming convention while transferring data from one clock domain to another clock domain.So based on that I can provide false path between nodes. Regards, Krupesh --- Quote End --- 50 MHz and 55MHz though related can't be synchronous for timing purpose. The tool may compute worse pattern. So you need CDC (using fifo is safe). You can provide false path if you have double synchroniser and taken care of data transfer
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
You want to use this construct in your .sdc file:
set_clock_groups -asynchronous -group { CLOCK_50 } -group { CLOCK_55 } to eliminate interclock timing constraints.- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Thanks Kaz and ak6dn
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
--- Quote Start --- 50 MHz and 55MHz though related can't be synchronous for timing purpose. The tool may compute worse pattern. So you need CDC (using fifo is safe). You can provide false path if you have double synchroniser and taken care of data transfer --- Quote End --- There is a danger when using false paths across domains like this that, in theory, the fitter could place the CDC registers on opposite sides of the chip, which would be a problem. Often it is better to use a max delay instead of a false path. Something that should make it easy for the tool to route but not do something stupid.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
--- Quote Start --- There is a danger when using false paths across domains like this that, in theory, the fitter could place the CDC registers on opposite sides of the chip, which would be a problem. Often it is better to use a max delay instead of a false path. Something that should make it easy for the tool to route but not do something stupid. --- Quote End --- yes I have heard of that, and too much delay affects MTBF. However the tool detects synchroniser chains and it should be their responsibility not to put the registers miles away but yes I will use max delay instead of false path.
Reply
Topic Options
- Subscribe to RSS Feed
- Mark Topic as New
- Mark Topic as Read
- Float this Topic for Current User
- Bookmark
- Subscribe
- Printer Friendly Page