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Altera_Forum
Honored Contributor I
736 Views

How to know or test the delay time of each logic unit

I am making delay line to implement the TDC. I tried to use buffers to make the delay line and want to know the delay time of each buffer element. But when I use the TimeQuest to report the path delay, it seems that no matter how many buffers I add, the delay times are the same. For example, I use 8 buffers and 4 buffers separately, the pictures and report are showed below. 

 

http://www.alteraforum.com/forum/attachment.php?attachmentid=13069&stc=1  

http://www.alteraforum.com/forum/attachment.php?attachmentid=13070&stc=1  

http://www.alteraforum.com/forum/attachment.php?attachmentid=13071&stc=1  

 

I guess because the IO buffers consume two much time compared to the buffers B-I (B-E), so the delay time of the buffers are ignored. 

 

So, my question is how to know the delay time of each logic unit in a specific FPGA family? For example, if I use buffers, then the delay time of each buffer must be known, and if I use the carry line to make the delay line, I must know the delay time of each adder. Thanks for any help.
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4 Replies
Altera_Forum
Honored Contributor I
29 Views

Have you checked that quartus hasnt reduced your logic into a single wire? unless you explicitly ask it not to, it will reduce all buffers like this. You can do this via the keep attribute in your HDL. 

 

The next problem is that while timequest can give you the worst case delay, the timing delay through all logic elements in modern FPGAs is very small to start with, and then they vary with PVT - process, voltage and temperature, so it is very difficult or impossible to get a known time delay through logic. FPGAs are designed around a synchronous archutecture.
Altera_Forum
Honored Contributor I
29 Views

Thanks. I will check it later. If it is hard to know time delay by logic, do you know other ways to measure the delay time? I am making the TDC to measure the time duration of the signal. If I don't know the delay time of each unit, I can not calculate the time duration of the signal even if I know how many delay units a signal pass. Do you have other suggestions?

Altera_Forum
Honored Contributor I
29 Views

What order of length for signals are you expecting? can you not just run a fast clock and measure the length of a signal using a counter?

Altera_Forum
Honored Contributor I
29 Views

My objective is to make a fine time measurement TDC with ps order, so the counter's resolution is not enough. But thanks for your answer, I will try other methods. May be the oscilloscope can be used.

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