Hello everyone. I have a simple multiplexing design that I have created using Block Diagram/Schematics in Quartus II. Now, I want to simulate the design using (modelsim-altera 10.1d) instead of Quartus Simulator because the ModelSim has many more features. But even after converting the Blocks into VHDL code and compiling them successfully in ModelSim, when I run the Simulation I don't get any output. Could you please help me with this???? I would really appreciate it. My output involves very large clock periods and it's impractical to use Quartus II Simulator. Thanks.
No, I'm afraid I haven't. How do I get that and is it necessary??? I mean can't I do a simple simulation without a testbench??? In fact that's the very reason why I went to Block Diagram/Schematics. Because I don't have to write the VHDL codes. I appreciate your help.
The test bench at a minimum is needed to drive the inputs. Even if it it just dives constants. Without a test bench , the will be no inputs, so there will probably be no output.