How to make a FLAG using verilog

Altera_Forum · ‎07-27-2018

Dear Community,

I’ve two modules – on is parsing the USART RX signal and the other one is a state machine which shall do something else in case the first module founds e.g. the word “read” inside the usart stream.

In my first attempt I tried to use an inout wire that is connected with two regs, one inside the first module “USARTDecoder” and the other one inside the second module “Branch”. However if I compile the stuff I get a fan out error for obvious reasons.

I would be very glad if someone could suggest a way how to implement a flag – like wire/reg that can be accessed/set and reset by two modules e.g. for

synch puposes.


module USARTDecoder_READ_OKsignal(trigger, signal_in, capture, clk) ;//capture_reset,clk);
input trigger;
input    clk;
input   signal_in;
inout  capture;
//input  capture_reset;
parameter p1 = "r"; 
parameter p2 = "e"; 
parameter p3 = "a";
parameter p4 = "d";
reg counter;
reg trigger_locked;
reg reg_capture;
initial trigger_locked = 1'b0;
initial reg_capture = 1'b0;
//trigger: _____|-|_____  is high while the stop byte is receives by receiver
always @(posedge clk) //use a clock higher than usart 
begin
if(trigger == 1'b1 && !trigger_locked) begin
                                             counter <= counter + 8'd1; 
               trigger_locked <= 1'b1; // lock the addition (make ssure there is only one addition per trigger
end
if(trigger == 1'b0 ) begin                      
   trigger_locked <= 1'b0; // unlock lock for a subseqeunt addition    
end
case (counter)
  0: begin 
    // stay here until the fist byte arives
 //  if(capture_reset)  reg_capture <= 1'b0; 
     end
   //stopbyte addition turns counter to 1 
  1:if(p1 == signal_in) counter<= counter + 8'd1;
  else counter <= 8'd0;
   //received byte equal to requested byte turn counter to 2
 // next stopbyte turn counter to 3 etc.
  3:if(p2 == signal_in) counter<= counter + 8'd1;
  else counter <= 8'd0;
  5:if(p3 == signal_in) counter<= counter + 8'd1;
  else counter <= 8'd0;
  7:if(p4 == signal_in) begin
                                reg_capture <= 1'b1; //set capture high until it is reset by another process
  counter <= 8'd0;  // back to zero with the next clock cycle 
 end
 else counter <= 8'd0;  
 endcase;
end //posedge always on clk 
assign capture = reg_capture;
endmodule 
module Branch(write, read, channela, channelb, out, clk);
inout write,read;
//output write_reset;
//output read_reset;
input clk;
input channela;
input channelb;
output out;
reg reg_out;
reg reg_write,reg_read;
initial reg_out = 16'd0;
initial reg_write = 1'b0;
initial reg_read = 1'b0;
always @(posedge clk) //use a clock higher than usart here 
begin
if(write) begin
reg_out = channela;
reg_write <= 1'b0;
end
if(read) begin
reg_out = channelb;
reg_read <= 1'b0;
end
end
assign out = reg_out;
//assign read_reset = reg_read;
//assign write_reset = reg_write;
assign read = reg_read;
assign write = reg_write
endmodule

benc · ‎07-30-2018

The code is hard to read, so I did not read it in details. As for the question, normally you would instantiate a register with synchronous set and reset signal. Then you would create these set and reset signals in other synchronous processes (different modules in your case).