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How to make all Verilog files being recognized as SystemVerilog files?

Altera_Forum
Honored Contributor II
‎01-18-2017 10:21 AM
1,791 Views

Hi All, 

 

How to make all Verilog files in the Quartus-II Project being recognized as SystemVerilog files?  

 

Could it be done in the Project Settings? Where? Is there some special TCL command?  

 

Thank you!
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Altera_Forum
Honored Contributor II
‎01-18-2017 10:58 AM
821 Views

Under 'Project' -> 'Add/Remove files in project', select each file in turn, click 'Properties' and change the 'Type'. 

 

Alternatively, change all your file extensions to .sv and Quartus will automatically assume they're System Verilog. 

 

Cheers, 

Alex
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Altera_Forum
Honored Contributor II
‎01-18-2017 12:32 PM
821 Views

Is there a TCL command for this purpose?

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