How to manually place a component with Quartus II

[Altera_Forum]

How do you manually place a component on a FPGA with Quartus ? i.e. I have the coordinates where I want to put the component on the FPGA, how do I use them with my VHDL code to say to Quartus 'put the component at these coordinates (x,y)' ? Thanks !

[Altera_Forum]

You will need to identify the specific LUT or register path first. When you have the path name, you can use TCL or modify your QSF file to add something like this: 

 set_location_assignment FF_X1_Y48_N37 -to "entity_name:instance_name|specific_register"  You cannot just add signal names, the path must map exactly how Quartus format's it, AND what it named the register/LUT. It may have created duplicates or merged several registers into one. An assignment to a node that doesnt exist will just generate a warning in quatus, not an error. The best thing to do is use the nodefinder and copy the path of the nodes you want to lock. You can also restrict placement to specific regions within the device. something like the following:  set_global_assignment -name LL_ENABLED ON -section_id some_region# You can turn it on and off  set_global_assignment -name LL_AUTO_SIZE OFF -section_id some_region# You can let the fitter try and auto size the region to fit the logic in for you (usually want this off unless exploring options  set_global_assignment -name LL_STATE LOCKED -section_id some_region# Locked in a specific X,Y location, otherwise set to "FLOATING"  set_global_assignment -name LL_WIDTH 3 -section_id some_region set_global_assignment -name LL_HEIGHT 2 -section_id some_region set_global_assignment -name LL_ORIGIN X38_Y63 -section_id some_region set_instance_assignment -name LL_MEMBER_OF some_region -to "entity_name:instance_name|sub_entity_name:sub_instance_name|*" -section_id some_region  All these assignments accept wildcards * and ?. * replaces unlimited characters and ? replaces a single character. All this can be added/modified from the floorplanner.  Is there any particular reason you want to lock specific registers and LUTs? Its a tedious process and unless you have a design thats having difficulty meeting difficult timing because its spreading entities all over the chip - it is usually not worth bothering. The fitter will usually do a better job than you.

[Altera_Forum]

Ok thank you very much Tricky, I'll try to do this !

[Altera_Forum]

You can do it using Quartus Backannotate feature. 

 First compile your design (synthesis + fit). Then enable backannotate in Assignments-> Back Annotate Assignments dialog. Save the project. Quartus will add all nodes of your design along with their locations: LABs, FFs, PLLs, Transceivers.  Find the node you're interested in, and changed to the desired location. Remove the rest of the backannotated constraints.  Thanks, Evgeni

[Altera_Forum]

Ok thanks OutputLogic. 

I tried your way and it almost works. Indeed, the optimizer simplified my circuit, changing the nodes. Therefore I cannot change the location of the nodes I want.  Dou you know if there is a way to lock an architecture (like a "don't touch" in the .qsf) or disable the optimizer ( it seems I cannot find the option in the settings)?  Thanks

[Altera_Forum]

You can add attributes in your HDL to prevent it from merging registers. This is useful when you have a register with a high fanout, so you want two separate registers. A VHDL example is below: 

  ATTRIBUTE maxfan : NATURAL; ATTRIBUTE dont_merge : BOOLEAN; ATTRIBUTE noprune : BOOLEAN; ATTRIBUTE syn_keep : BOOLEAN; signal a,b,c : std_logic; attribute maxfan of a : signal is 10; attribute maxfan of b : signal is 5; attribute dont_merge of a : signal is true; attribute dont_merge of b : signal is true; attribute dont_merge of c : signal is true; ... --clocked process: a <= ip; b <= ip; c <= ip; --etc.

[Altera_Forum]

You can also turn off synth settings for individual registers : 

  ATTRIBUTE altera_attribute : STRING; ATTRIBUTE altera_attribute of my_shift_register : SIGNAL is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";

[Altera_Forum]

Thanks Tricky, I'll try it. Meanwhile, I'd like to know something else. 

 I'll tried the first thing you said to manually place a component. And I have a new problem. I created a component, and instead of looking for the name of each sub-component, I instantiated the global component with my own name, so I can place it naming the global component in the .qsf . My problem now is that my component takes more than one 'LAB' cell, as you can see in the file attached. So when I write this code line in the .qsf file :   set_location_assignment LAB_X9_Y49_N0 -to inst_test   Quartus ignores the line since the location specified is too small for my component. Is there a way for me to solve the problem ? Because when I did that, I thought that when Quartus instantiates a global component, it uses a sub-component as a reference for the placement, and I just had to specify its location, and Quartus deduces itself the location for the other sub-component.

[Altera_Forum]

Instead of assigning it to a single LAB, create a region that contains enough LABs to fil the component, and then add the component to the region.  

 There are other settings that allow the fitter to "overspill" the region if there isnt enough logic available (but this wont happen if there are not enough RAMs or Multipliers - you just get an error) or just force it to use only the logic in the region. Its much easier to modify regions from the GUI than from the .QSF (however, the QSF gets a bit messy as it keeps moving your assignments arround, and changes are appended at the bottom).

[Altera_Forum]

Thank you very much Tricky. Here is what I wrote in the .qsf : 

 set_global_assignment -name LL_ORIGIN X38_Y63 -section_id some_region set_global_assignment -name LL_STATE LOCKED -section_id some_region set_instance_assignment -name LL_MEMBER_OF some_region -to inst_test -section_id some_region  I didn't define the size of the region so Quartus uses AUTO_SIZE to define it itself. Because the idea for me is not to know the size of my component and let Quartus define automatically the size of the region according to it. But I used the STATE LOCKED to be sure that the region will be placed at X38_Y63.  My problem now is that AUTO_SIZE ON and STATE LOCKED are two conflictory commands. Here is the Quartus' warning :  Warning (140021): LogicLock region "some_region" cannot be auto-sized and have a locked location at the same time  Indeed, in those conditions, Quartus apparently ignores the STATE LOCKED and places my component wherever he wants (when I look to the Chip Planner, the component is in the region, but the region is not at X38_Y63). Whereas my goal here is not to know the size of my component (i.e. how many LAB cells it needs) but to place it where I want. That's why I want to use AUTO_SIZE and STATE LOCKED at the same time. Any idea?

[Altera_Forum]

The reason you cannot have both, is that if you place the region near the edge, it cannot auto size properly.  

The silly thing is, auto size is a bit silly really, as it takes away from the whole point of having a region.  What I have done in the past is just give it a region so it constrains the component within a certain area. If you dont know the size of the component, then you shouldnt be constraining it to a region. The whole point of the region is that you already know the size of the component (roughly).  The auto size is meant to give you an idea of the space needed before you lock it down. But its generally rubbish it autosizing (my previous attempts using this tended to create a region half the size of the chip!)