How to negedge trigger the IP module?

[Altera_Forum]

In Quartus II, it seems all the sequential IP modules are triggered by postive edge. If I want to trigger them using negative edge, how can I do except I put a not gate in clock? 

 I don't think add a not gate is a good idea since it will bring delay which may affect the design which has high rate clock.

[Altera_Forum]

You can use pll to generate 90degrees shifted clock. I guess there is no other way, unless the ip core is not encrypted.

[Altera_Forum]

I think you are right. Pll can provide exact 90 degree shift clock. We can't edit ip core.  

Thanks very much.