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Beginner
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How to package a custom IP containing IP as submodule

Hi,

 

I have created simple design where I instantiate LPM_sub_add IP as submodule. I would like to package the whole top level so that I can reuse IP. Below are the steps used:

  1. Create a new component in Platform designer.
  2. I added the .qip file of the IP along with top VHDL file in the synthesis files.

While generating the complete IP I am seeing bunch of errors:

Error: Component add1 can't instantiate a custom component with the same name as itself

Error: add1.add1_0.add1_0: Component add1 1.0 not found or could not be instantiated

Error: add1.clk_0.clk/add1_0.clock: Missing connection end (try "Remove Dangling Connections")

Error: add1.add1_0: add1_0.clk must be connected to a clock output

Error: add1.add1_0.add1_0: Component add1 1.0 not found or could not be instantiated

Error: add1.clk_0.clk/add1_0.clock: Missing connection end (try "Remove Dangling Connections")

Error: add1.add1_0: add1_0.clk must be connected to a clock output

Error: add1_0: missing_module does not support generation.

Error: qsys-generate failed with exit code 1: 4 Errors, 3 Warnings

 

I guess somehow I have to stitch the netlsit but not sure though. I am not sure if I am missing something basic here. Can someone please guide me with the exact steps to package a custom IP which has submodule IPs?

 

Thanks,

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Moderator
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You cannot add IP files to the platform designer when developing the custom IP.

 

What you need to do is use composition. You can refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-platform-designer... page 617 for that.

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Beginner
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Thanks for your reply @KennyT_Intel​ How can I use this Tcl command in the platform designer? Does the platform designer have Tcl console?

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Beginner
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@KennyT_Intel​  let me elaborate the issue. I have attached a simple test case where I have instantiated LPM_sub_add IP. I want to package the entire led_comp module. It means I have to package the entire system which includes the IP.

According to your reply, I think I should add the Tcl command in hw.tcl. However, I am confused, how can I pass information regarding port map. Can you please provide elaborate steps on how to proceed for the same. My actual implementation is on a big project. If you can guide me for this simple testcase, then that will provide me reference for the main design. Thanks for your help in advance.

 

Do you have service portal where I can raise a request?

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Moderator
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Sure. give me some time to look into this and I will get back to you next week.

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Moderator
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For your question:

 

Do you have service portal where I can raise a request?

Answer:

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base...

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Moderator
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Hi

 

You can check your email, I posted an example for you on how to do it.

 

Thanks

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Beginner
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@KennyT_Intel​  thanks a lot for your design file. But unfortunately I am unable to open the file as I dont have the device installed. I am using quartus prime 17.1 with device Cyclone V 5CGXFC7C7F23C8. Is it possible to share the design file for the mentioned device and version of the tool?

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Beginner
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where can I find the properties of the IP to be used as Tcl command? Is there a file generated that can guide me?

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Moderator
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I will resend you the design.qar.

 

For the properties of the IP, you will have to look into the specific IP user guide.

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Moderator
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I look into the design.qar again, it will be better that I dont modify it as a lot of properties are tied to Arria 10. What I suggest is you download and install this device in

 

http://fpgasoftware.intel.com/18.1/?edition=standard&platform=linux

 

Choose the version that you want and click individual files. From there you can choose the specific device to be download qdz files.

 

After that, in Quartus, just click tools -> install device to install the arria 10 device.

 

 

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Beginner
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Hi @KennyT_Intel​ 

I tried Looking into the https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_fifo.pdf for FIFO. I could not find the exact Parameters you are mentioning. It's neither intutive nor straightforward. Can you please share if there is some file I can use as reference to write These Parameters.

set_instance_parameter_value mfifo GUI_AlmostEmpty "false"

set_instance_parameter_value mfifo GUI_AlmostEmptyThr "1"

set_instance_parameter_value mfifo GUI_AlmostFull "false"

set_instance_parameter_value mfifo GUI_AlmostFullThr "1"

set_instance_parameter_value mfifo GUI_CLOCKS_ARE_SYNCHRONIZED "0"

set_instance_parameter_value mfifo GUI_DISABLE_DCFIFO_EMBEDDED_TIMING_CONSTRAINT "true"

set_instance_parameter_value mfifo GUI_ENABLE_ECC "false"

set_instance_parameter_value mfifo GUI_Empty "true"

set_instance_parameter_value mfifo GUI_Full "true"

set_instance_parameter_value mfifo GUI_LE_BasedFIFO "false"

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Moderator
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Did you follow the steps that I provided u in the mail? Basically, when you generate the IP. Under the *.qip, it had somethings like .v files that consist of the defparam parameter for you to used.

 

Unfortunately, we don't have documentation for the specific Ip that you want. https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_low_level.pdf?wapkw=D...

 

But if you make the generation of the IP, you should see one of the files have the defparam for you to be used.

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Moderator
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Is there any update from yourside?

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Beginner
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@KennyT_Intel​ ,

I am still stuck at this point. The design i am trying to port has native phy, generic fifo which are not available as part of the platform designer. Even though I am using all Intel IPs I am unable to migrate the design to platfrom designer. Its really annoying. As you told that "But if you make the generation of the IP, you should see one of the files have the defparam for you to be used.", can you tell me the exact file name and the location where it can be found?

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Moderator
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Hi Arpan,

 

Can we have a skype to look into this? I had send you an email. You can check your inbox.

 

Best regards,

Kenny

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Beginner
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@KennyT_Intel​  what is the Status of the skype call? I am waiting for your response since 8days.

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Moderator
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Arpan, thanks for having a skype last week. Will work with you on following skype on 26/12/19.

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