I found that Quartus prime does not do any logic optimization/minimization compared to other synthesis tools like mentor's precision or synplify. I am using the lite edition and defaults in the project settings
Quartus does a LOT of logic optimization. How can you say it 'does not do any optimization/minimization'? That is NOT my experience at all.
Logic functions (like A or not A) will be reduced to constants and folded into the equations. Logic that generates unused functions will be eliminated.
So I completely disagree with your statement.
i cannot agree:
module infer (
output wire q,
input wire a, b
assign q = (a & ~b) | (a & b);
q in this equation should = a, but here is the net schematic:
The resource utilization can be optimized by using different setting in compiler as below:
Click Assignments ➤ Settings ➤ Compiler Settings ➤ Advanced Settings (Synthesis)
You can select the optimized setting for your design.
Looks like you are using the 'RTL Viewer'. It displays your SOURCE RTL as a schematic. So it is displaying exactly what you entered, as expected.
If you want to see the effects of logic synthesis/optimization, open the POST MAPPING or POST FITTING views from that same menu.