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AYoun22
Beginner
196 Views

does quartus prime do logic optimization/minimization, like a+~a will be replaced by 1?

I found that Quartus prime does not do any logic optimization/minimization compared to other synthesis tools like mentor's precision or synplify. I am using the lite edition and defaults in the project settings

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8 Replies
ak6dn
Valued Contributor II
60 Views

Quartus does a LOT of logic optimization. How can you say it 'does not do any optimization/minimization'? That is NOT my experience at all.

Logic functions (like A or not A) will be reduced to constants and folded into the equations. Logic that generates unused functions will be eliminated.

So I completely disagree with your statement.

AYoun22
Beginner
60 Views

i cannot agree:

 

module infer (

output wire q,

input wire a, b

);

 

assign q = (a & ~b) | (a & b);

 

endmodule

 

q in this equation should = a, but here is the net schematic:

 

net.png

MEIYAN_L_Intel
Employee
60 Views

Hi,

 

The resource utilization can be optimized by using different setting in compiler as below:

Click Assignments ➤ Settings ➤ Compiler Settings ➤ Advanced Settings (Synthesis)

 

You can select the optimized setting for your design.

 

Thanks

ak6dn
Valued Contributor II
60 Views

Looks like you are using the 'RTL Viewer'. It displays your SOURCE RTL as a schematic. So it is displaying exactly what you entered, as expected.

If you want to see the effects of logic synthesis/optimization, open the POST MAPPING or POST FITTING views from that same menu.

AYoun22
Beginner
60 Views

it looks like this is the way. yes those views provide the optimized / final views.

 

thanks

sstrell
Honored Contributor II
60 Views

"POST MAPPING or POST FITTING views from that same menu."

 

Referring to the Technology Map Viewer here instead of the RTL Viewer.

 

#iwork4intel

AYoun22
Beginner
60 Views

yes, this works

MEIYAN_L_Intel
Employee
60 Views

Hi,

 

Thank you for your update.

 

Thanks

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