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Altera_Forum
Honored Contributor I
1,234 Views

How to put an additional sub circuit to physically different locations in FPGA?

Hello, 

I am researching on detecting Hardware Trojan, so I have 2 different designs: 

1. Original circuit 

2. Original circuit + Hardware Trojan (added into original circuit source code). 

So I have a couple of following questions: 

a. My detection method is sensitive to changes in layout. Is there anyway that after adding hardware trojan to the original circuit code and recompiling it, I can keep the placement and routing (layout) of the original circuit part is exactly the same as before adding anything. I mean all the resources used, the physical location and routing should be the same for the original part of the new circuit. The only change should be the additional hardware trojan is placed somewhere, physically and connected to the original circuit? 

b. Can I change the location of the hardware trojan? Like put it in the left corner or right corner of the FPGA, move it further or closer from the original circuit ?? 

 

 

I am thinking of using ECOs, but it seems to be very complicated and take a lot of time and I don't know how to use it yet. 

 

Thank you so much and I am looking forward to hearing from you guys.
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4 Replies
Altera_Forum
Honored Contributor I
40 Views

You can use Logic Lock, design block reuse, and optionally partial reconfiguration to accomplish all of this. Look at Arria 10 or Cyclone 10 since these features (except for Logic Lock) require the Pro edition of the Quartus Prime software.

Altera_Forum
Honored Contributor I
40 Views

 

--- Quote Start ---  

You can use Logic Lock, design block reuse, and optionally partial reconfiguration to accomplish all of this. Look at Arria 10 or Cyclone 10 since these features (except for Logic Lock) require the Pro edition of the Quartus Prime software. 

--- Quote End ---  

 

 

Hello, thank you so much for your reply. I only have Cyclone V and Quartus Prime free (web) version. Is there any other ways to achieve that ?
Altera_Forum
Honored Contributor I
40 Views

You can still use Logic Lock and look at the incremental compilation feature.

Altera_Forum
Honored Contributor I
40 Views

 

--- Quote Start ---  

You can still use Logic Lock and look at the incremental compilation feature. 

--- Quote End ---  

 

Thank you so much for your help. 

 

https://alteraforum.com/forum/attachment.php?attachmentid=14708&stc=1 https://alteraforum.com/forum/attachment.php?attachmentid=14709&stc=1  

Another question is that: I have the placement of my design on chip planner, how can I determine where they are placed physically in FPGA (board) ? Like I know where the pins are physically on the FPGA (board), but I am not sure which corner in the chip planner image is according to which corner of the FPGA physically in the real board.  

Hope that I did make the question clear. 

Thank you so much!
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