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Altera_Forum
Honored Contributor I
1,364 Views

Problem in using the same module in project for many times

Hi everyone, 

 

I am trying to use one module for several times in one project cause I want to control several ADCs using one main project. 

 

And my way to do it is like this: 

ADC ADC1(.RST2(RST2),.DOUT(DOUT1),.SCLK(SCLK1),.DIN(DIN1),.CLK(CLK),.OUTDATA(OUTDATA1)); ADC ADC2(.RST2(RST2),.DOUT(DOUT2),.SCLK(SCLK2),.DIN(DIN2),.CLK(CLK),.OUTDATA(OUTDATA2)); 

 

There are only some meaningless warnings when I run this program in quartus. What's more, I am sure that the ADC code works very well.  

 

When I only use one ADC module, for example: ADC ADC1(.RST2(RST2),.DOUT(DOUT1),.SCLK(SCLK1),.DIN(DIN1),.CLK(CLK),.OUTDATA(OUTDATA1));//ADC ADC2(.RST2(RST2),.DOUT(DOUT2),.SCLK(SCLK2),.DIN(DIN2),.CLK(CLK),.OUTDATA(OUTDATA2)); 

 

The result is perfect when I download it to my board. Same if I comments the second line. 

 

However, if I am trying to control this two together, I cannot get good results from the board. 

 

Is there any one can help me? Thank you very much! 

 

Yours 

Yonghang
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10 Replies
Altera_Forum
Honored Contributor I
41 Views

P.S. My FPGA board is ALTERA DE2 Cyclone 2 series.

Altera_Forum
Honored Contributor I
41 Views

That is sign of timing problems, if unreported timing failures then your io constraints could be wrong. With more logic fitting and routing changes.

Altera_Forum
Honored Contributor I
41 Views

you also need to check you are indeed configuring all ADC correctly when more than one.

Altera_Forum
Honored Contributor I
41 Views

Hi kaz,  

 

Thank you for your reply. As I said, the code works well when I only test one module, so I think there is no problem with io assignment. I will check other things. 

 

Thank you very much! 

 

Yours 

Yonghang Tian
Altera_Forum
Honored Contributor I
41 Views

Hi kaz, 

 

Do you think it is OK for me to control these ADCs at the same time? I have checked other things and there are no problem, so I think that it is really my timing problem. And I have no idea how to correct the problem. 

 

Quartus said nothing important but told me that I did not assign DOUT1 and DOUT2( they are output of ADCs) as clocks(I got this warning when I were testing one ADC, and it did not matter). 

 

My .sdc file is like this:create_clock -name F_CLK -period 20ns -waveform {0 10} derive_pll_clocks create_generated_clock -name CLK_REG -divide_by 20 -source }] derive_clock_uncertainty create_generated_clock -name CLK -divide_by 1 -source set_output_delay -clock CLK -clock_fall -max 950ns set_output_delay -clock CLK -clock_fall -min 50ns set_output_delay -clock CLK -clock_fall -max 950ns set_output_delay -clock CLK -clock_fall -min 50ns  

 

The only two warning I got from quartus are listed below: 

Warning (332060): Node: DOUT1 was determined to be a clock but was found without an associated clock assignment. Warning (332060): Node: DOUT2 was determined to be a clock but was found without an associated clock assignment.  

 

Yours 

Yonghang Tian
Altera_Forum
Honored Contributor I
41 Views

What are DOUT1 and DOUT2 connected to? Quartus thinks they are clock paths. Have you run a clocks report in TimeQuest to see if your clocks are set up correctly?

Altera_Forum
Honored Contributor I
41 Views

Sorry, I did not explain my problems clearly. So, DOUT1 & DOUT2 are outputs of two ADCs. They are used to trigger my microcontroller to read the output. I think that is why quartus treats DOUT as a clock, and SCLK is the clock I sent to ADC(not a real clock, only when DOUT is vivid, SCLK equal to CLK; or SCLK is 0). DIN is to set the configuration registers in the ADC.  

 

I have run a clocks report in timequest and there is no problem except the warning I posted before. By the way, .sdc file had no problem when I was testing one ADC.  

 

I am using ADS1018 by TI.
Altera_Forum
Honored Contributor I
41 Views

Your naming is a little confusing! So DOUT1 and 2 are *inputs* to the FPGA and DIN and SCLK are *outputs* from the FPGA. DOUT1 and 2, if they are driving clock inputs, should be set up as base clocks with the create_clock command.

Altera_Forum
Honored Contributor I
41 Views

Hi sstrell,  

 

I fixed this problem. It is not because of timing requirement, it is because I use the same clock input(CLK, shown in my code before) for this two ADCs. Actually these two ADCs can not work at the exactly same time. so they can not share the same clock. 

 

I will set DOUT as a basic clock to decrease that warning! DOUT is a combined pin, if there is no new data from ADC, DOUT acts as ready signal. Once there are new datas from ADC, DOUT trigger my board to send in SCLK and read data out. 

 

Thank you very much for your advise. 

 

Yours 

Yonghang Tian
Altera_Forum
Honored Contributor I
41 Views

 

--- Quote Start ---  

Hi sstrell,  

 

I fixed this problem. It is not because of timing requirement, it is because I use the same clock input(CLK, shown in my code before) for this two ADCs. Actually these two ADCs can not work at the exactly same time. so they can not share the same clock. 

 

I will set DOUT as a basic clock to decrease that warning! DOUT is a combined pin, if there is no new data from ADC, DOUT acts as ready signal. Once there are new datas from ADC, DOUT trigger my board to send in SCLK and read data out. 

 

Thank you very much for your advise. 

 

Yours 

Yonghang Tian 

--- Quote End ---  

 

 

 

Hi, yonghang, 

 

Congratulations on you make it! And I meet the same problems, I configured the same three ADCs module in my project, see in the following, 

sample sample_adc1( 

.clk(clk), 

.rst_n(rst_n), 

.miso(miso1), 

.mosi(mosi1), 

.csn(csn1), 

.sclk(sclk1), 

.data(data1) 

); 

 

sample sample_adc2( 

.clk(clk), 

.rst_n(rst_n), 

.miso(miso2), 

.mosi(mosi2), 

.csn(csn2), 

.sclk(sclk2), 

.data(data2) 

); 

 

sample sample_adc3( 

.clk(clk), 

.rst_n(rst_n), 

.miso(miso3), 

.mosi(mosi3), 

.csn(csn3), 

.sclk(sclk3), 

.data(data3) 

); 

 

//clk--input external clock 25MHZ, 

rst_n--reset  

miso--AD7888 output sample data to FPGA 

mosi--FPGA output configure data to AD7888 

csn--chip select  

sclk--FPGA output serial clk to AD7888 

 

my problem is : when I only use one ADC in my project , the result is correct , but when I use two or three ADCs module , There is interference between the data (I use in system sources and probes editor to watch the result), 

thus i can't get all correct data and get warning messages: 

Warning (332060): Node: sample:sample_adc3|csn was determined to be a clock but was found without an associated clock assignment.  

...........................................(much) 

 

I changed the clk , using three output clock form PLL module, but i seems no difference, I need your help! THANKS!
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