How to set path skew through SDC?

[D22]

Hi!

I'm trying to develop a sort of TDC (Time-to-Digital Converter) using the carry-chain in a Cyclone device. In particular, I’m focusing on the fine measurement that, for my application, could have a resolution about 100-200 ps. I used the Design partitions and LogicLock region to physically divide my project in sections . The problem is the mismatch between paths that can be very huge!

How can I set the skew between paths and what skew resolution it can be achieved?

Are set_max_delay, set_net_delay, ect the only way to do this?

[KhaiChein_Y_Intel]

Hi D22,

You may use set_max_skew

Reference: https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#tafs/tafs/tcl_pkg_sdc_ext_ver_1.0_cmd_set_max_skew.htm

[D22]

Hi KYeoh,

thank you for answer. I tried this and other SDC command, but the skew is still high. Is it possible to achieve a skew about 100 ps between paths? For example, I have 2 block, A and B. There are 32 paths from block A to block B. I assign a LogicLock region to each block. Can I set the fitter to have a difference of 100 ps between each of 32 paths from A to B?

[sstrell]

I'm assuming (or presuming) that these paths have registers on both ends. What speed are you running both sides at and you have constrained the clocks correctly? Have you tried seeing what results you get when you don't use Logic Lock? Remember that LL is basically another constraint on the Fitter, which could prevent it from choosing optimal placement and routing.

[D22]

Hi sstrell,

thank you for answer and advices. My project uses a 200 MHz clock internally generated by a PLL starting from a 50MHz external clock. I have constrained the input clock through the “create_clock” SDC command and the PLL output clock through the “create_generated_clock” command. For my project, some LL block are necessary. However, I can try to remove the not-strictly-necessary LLs.

Come back to block A and B. The block A is a generic block (it does something) while the block B is a decoder with the outputs registered. I assign a LL to block A and B. By this way I can see the decoder-registers as a block. Can I match the paths from outputs of the registers of block A (i.e. the outputs of block A) to inputs of block B? I also tried to use registers at the inputs of the decoder, but I can’t match the paths yet (from the outputs of block A registers to the inputs of block B registers).

[KhaiChein_Y_Intel]

May I know what do you mean by match the path?

[D22]

I mean have the same delay of all the paths from outputs of block A to inputs of block B. For “same delay” I mean with a resolution of 50-100 ps. For example, the path from output[1] of block A to its input of block B has a delay of 1.100ns, output[2] of 1.150 ns, etc. Is it possible?

I think it is not possible to reach that resolution, but what solution is possible?

[KhaiChein_Y_Intel]

Hi D22,

If you want to set the delay from output_A[1] to input_B[1], you may use set_max_delay or set_min_delay.

If you want to set skew between path A[1]-B[1] and A[2]-B[2], etc, you may use set_max_skew.

The software will place and route based on the constraints. If you set some logic lock in the design, it will place and route within the region you have set. This might not be the optimal placement and routing.

Thanks.

[D22]

Hi KYeoh,

thanks a lot for advices. I tried both set_max_delay (and set_min_delay) and set_max_skew. In particular, the latter is what I need, but the skew detected in TimeQuest is greater than the one set with this sdc command. 

[KhaiChein_Y_Intel]

Hi D22,

Could you check if this constraint is being ignored due to some reasons (e.g, incorrect syntax...) ?

Thanks