How to set zero delay path with Quartus II?

Altera_Forum · ‎10-11-2010

Hi, I'm pretty new to Verilog and I'm using Quartus II to try to achieve a zero delay path. I want to add certain delay to some non-free running clock/signal in order to become zero delay path, how to implement it?

And I also need your kind help to clarify on some syntax.

1. Y< = X & X & X & X; ç will this code be optimized to become Y<= X?

2. How to disable optimization on one single line of code?

3. How to add fixed delay path to code?

Thank you very much for the help & support~

Hope anybody can help, thanks thanks~

baer

Altera_Forum · ‎10-11-2010

I think this is not the better way to achieve zero delay, even if you could control optimization, since the overall delay depends non only on synthesis but also on routing.

You'd better use timing constraints on that path and use timing driven synthesis.

I'm not a TimeQuest expert but you probably can do want you need using the set maximum/minimum delay contraints.

Regards