How to share settings among several QII projects

[Altera_Forum]

I have one board layout that is used for several different FPGA designs. I want to share the parts of the settings that are the same among all the designs. The concept I want is an 'include' capability for settings. For example, all the designs have the same IO assignments, voltage, location, enables--they're all on the same board. But each design uses its own source files to define its logic. 

 How can I share my device and pin assignments, programming options, and other common settings across all the designs? With many designs and many pins, it can be very difficult to keep everything in step if there's a pin name change.

[Altera_Forum]

BTW, my attempts to use QIP files went nowhere (without QII comment, however).

[Altera_Forum]

My approach is to: 

- define pin locations in source code, and use the same toplevel in multiple designs. - define common timing constrains in a .sdc file and include it in multiple projects.  For the other settings, I do not know how to do it, so I just diff the .qsf files

[Altera_Forum]

I have common toplevel.v and .sdc files. How do you force the pin assignment in Verilog?

[Altera_Forum]

have a look here  

 verilog pin assignments (http://www.altera.com/support/software/eda_maxplus2/synplty/intro/pin.html)

[Altera_Forum]

why not create some kind of "golden" project that you can copy for each design you want to run on the board? 

 beyond that you can just copy+paste settings between project .qsf files.

[Altera_Forum]

And the menu point: "Organize .qsf file" is really great !!! 

It allows minimizing the diff between files.

[Altera_Forum]

Thanks to all. Looks like source assigns and sdc files are about the only way to go.

[Altera_Forum]

@ amilcar  

yes, but i would realy like to have that quartus also sorts the qsf currently it only groups them but if you want to compare 2 qsf files for the same target design, contents inside a section can be mixed and they are not sorted (alphanumerical)  @ ggarner don't forget to use qip files, they can be realy helpful

[Altera_Forum]

I haven't been able to find what info will be used from a qip file. The first thing I tried was to put the majority of my setting into a qip and reference it. No device or pinouts! 

 Docs about how & when Altera file types are really used are severely lacking. The info on qip in help just indicates it is for setting search paths (but no detail on allowed usage), altho looking at them shows some more.

[Altera_Forum]

there's a whole manual on Quartus Setting Files (.qsf). 

 http://www.altera.com/literature/manual/mnl_qsf_reference.pdf

[Altera_Forum]

But almost not a word about QIP content!!!!

[Altera_Forum]

qip can be very usefull if you are going to use a module within different designs. 

sopc components can include the top level and the qip with all sub level files., no need to edit the sopc component just edit the qip the qip, as you said, tells quartus where to look for other files, add them to the project  but what i am still seeking for is, how to make shure a tcl listed in qip is executed  qip, i like them more and more each time i use them

[Altera_Forum]

So where did you learn of their capabilities? How do you learn more? Where do you learn their syntax and limitations?

[Altera_Forum]

that a typical engineer task, knowing where to look and then copy :-) 

each time i see a qip file, i take a look into it if there could be something i haven't seen yet limitations ? by try'n'error

[Altera_Forum]

Unfortunately, that is what I thought. But I had hope that Altera might have published something to reduce the mystery. Guess not. 

 Thanks, though.

[Altera_Forum]

this forum is a also a good place to find answers or ask for them 

the manual thepancake gave a link to, was new to me but i haven't searched for it yet as jakobjones already wrote in another thread, google is a good seach tool even for these informations unfortunately you are right as some information a not so simply visible, thats a reason why users here write documentations or how to's like for sdc

[Altera_Forum]

you could generate a DDR2/3 memory core, and take a look at the <variation_name>pin_assignments.tcl and edit to your liking. 

 there are also some neat reference designs around that create the project from source during every build. these projects pull in a qsf during their complication and could be edited to target your board. unfortunately i can't quite remember which ones do that.