How to simulate On-Chip Flash IP core

[atosun]

Hello,

in my design I have implemented an On-Chip Flash IP Core

But due to the altera_onchip_flash_block.v being encrypted

I cannot properly simulate my design.

My question is, is there a way to simulate the design or is this a licensing issue. For reference I use Quartus Prime (Version 21.1.0 Build 842 10/21/2021 SJ Standard Edition) and Riviera Pro (version 2023.10.106.9105 built for Windows64).

The way I simulate is by adding the qip file of the IP core to my Project Navigator, I compile my Design in Quartus and do Tools -> Run Simulation Tool -> RTL Simulation, where it automatically simualtes the design in Riveira Pro.

Any help would be appreciated. Thanks a lot.

Best

Atakan

[NurAiman_M_Intel]

Hi,

Did you follow the guidelines when simulating the FPGA?

https://www.intel.com/content/www/us/en/docs/programmable/683080/23-1/aldec-active-hdl-and-riviera-pro-guidelines.html

Regards,

Aiman

[NurAiman_M_Intel]

Hi,

Any further information needed for this case?

Regards,

Aiman

[NurAiman_M_Intel]

We do not receive any response from you to the previous answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you