How to simulate a differential input driving a PLL?

[Altera_Forum]

I have a differential clock reference driving the pll inside my design. The problem is that I see that the reference clock input to the pll megafunction is single ended. This leads me to believe that I need to infer or instantiate differential input for the clock somehow in my design.  

 Is there a way to infer this in verilog? Any other alternatives for me to connect the differential input to the pll clock reference?  Thank you much in advance. -sanjay

[Altera_Forum]

A differential in- or output can be represented by a single port bit in the HDL code. It becomes a differential signal by simply assigning a differential I/O standard in the pin planner or assignment editor.

[Altera_Forum]

Yes! Thanks. I did realized that. Unfortunately, the code base that I had all had _p,_n pair signals. So I thought I'd ask. 

  -sanjay

[Altera_Forum]

--- Quote Start ---  the code base that I had all had _p,_n pair signals.  --- Quote End ---   Depends on, what's the intended purpose of these signals. There are also special cases where pseudo-differential outputs are utilized. I was talking about the way, differential I/O would be used in reasonable HDL coding. Besides that, you have various other options, e.g. instantiating low-level primitives for differential I/Os and connecting them explicitely. You can find everything in the Quartus software and MegaFunction documentation, if you feel a need to use this stuff.