How to simulate in SystemVerilog with Altera-Modelsim

[Altera_Forum]

Does the free version of Altera-Modelsim support system-verilog verification? 

 I tried but as I changed the Simulation File Format to systemverilog, I can not launch Altera-Modelsim in Quartus and only got an error message like shown in the attachment...   Please help, thanks!   PS. My design file is pure legacy verilog with Altera IP but my testbench is written in systemverilog and I used systemverilog feature like class, randomizaiton and assertion in the testbench.   If Altera-Modelsim cannot, what other products would do this job?

[Altera_Forum]

Did you try starting Modelsim directly? 

 The Modelsim-Altera-Edition will allow you to process SystemVerilog, but it will not allow you to mix languages (VHDL + Verilog), so you have to generate things like SOPC system components in Verilog.  The full version of Modelsim and Mentor Graphics Questa supports mixed language design, SystemVerilog assertions, etc.  Cheers, Dave

[Altera_Forum]

Thanks. 

Will Modelsim support class feature and randomization feature that used in systemverilog testbench?

[Altera_Forum]

--- Quote Start ---   Will Modelsim support class feature and randomization feature that used in systemverilog testbench?  --- Quote End ---    Post a testbench that includes these features, and I will test them in the full edition of Modelsim.  Cheers, Dave

[Altera_Forum]

Thank you. I've figured it out.  

 Modelsim SE 6.5 supports sv features including class, assertion and randomization.

[Altera_Forum]

--- Quote Start ---  Thank you. I've figured it out.    Modelsim SE 6.5 supports sv features including class, assertion and randomization.  --- Quote End ---    Great!  Do you have any good references, suggestions on using these language features?  I've been using VHDL up until now, but the Altera verification suite uses SystemVerilog - but very poorly from what I have seen - they do not use classes, interfaces, etc. I think the limitation in their suite is likely due to the limitations in Modelsim Altera-Edition.  I purchased the two books;  "SystemVerilog for Design" 2nd Ed, Sutherland etc.  "SystemVerilog for Verification", 2nd Ed, Spear.  The latter discusses the features you are interested in.  I didn't look at UVM, OVM, VMM, and all the other TLAs (three-letter-acronyms) for test classes. Which one are you looking at - if any?  Cheers, Dave