lpm_latch makes quartus_map run much longer

[Altera_Forum]

I am integrating a netlist design which has about 40K latches with async clear or set. 

If I use LPM_LATCH for these latches then quartus takes very long to map. If I use simple LATCH but pull the async ctrls to the D and ENA pins then it finishes much faster. Obviously i would like to use the lpm_latch but I don;t know how to make the tool run fast. Please give some pointers.. I am using stratix iv and quartus 11.

[Altera_Forum]

With recent FPGA families(e.g. Stratix IV), latches can be only implemented as logic loops, because asynchronous functions except for clear have been removed from register capabilities. I don't however understand the difference between the LPM_LATCH and "simple LATCH" implementation.

[Altera_Forum]

Hello Sir, 

 Many thanks for a reply. Simple latch is just LATCH (.q , .ena, .d0  lpm_latch has this with aclr and aset.  I need aclr and aset to port my design.  How do i instantiate a latch with clear (without using a combinational loop)    --- Quote Start ---  With recent FPGA families(e.g. Stratix IV), latches can be only implemented as logic loops, because asynchronous functions except for clear have been removed from register capabilities. I don't however understand the difference between the LPM_LATCH and "simple LATCH" implementation.  --- Quote End ---  

[Altera_Forum]

I have to say - filling a Stratix IV with latches seems like a massive waste of money. Why are you using latches, and not registers?

[Altera_Forum]

I don't have a choice on what netlist i am given to integrate.