Hi all!First of all, I'm new at this community and designing digital circuits on a fpga using vhdl. I've write a simple vhdl code that implements simple logic function such as comperator. But I'd like to simulate it to understand that its correctly working. How can I do that? Note: Im using Quartus software to synthesis. Thanks for your replays.. :rolleyes:
Well, I am new at this too. I am using Quartus II web edition.First of all you need to compile the code. ( Processing -> Start compilation). When this is done. Open Simulator Tool (Processing -> Simulator Tool). Now Netlist has to be generated. Choose Functional in Simulation mode (Then click button on the right to generate). The next step to set the test bench. Click on the OPEN button in the simlator tool window. Then waveform window pops up. Double click on area below (Name and Value at 10ns squares). Insert node or Bus window pops up then click on Node Finder. Click on List button on new pop-up window. Choose the signals that you want to simulate. You can assign values on the signal by Right click on the signal name. Click save on the main window to save the configuration. Now go back to Simulator Tool. Click on Start to simulate. To see the result, just go back to waveform window. Hope this would give some ideas on how to simulate.