How to start a new design - best way

[Altera_Forum]

Hi all, atm at work I've some time and I would like to plan how to start all our future design. 

I would like to use all the "new" features of Quartus II in order to better design our future chips.  I tell you what I would like to insert and the reason why I would like to. First of our design at the moment employ 3 different people. The design can be divided in 3 big block: 1- input stage 2- compute stage 3- Nios processor and code  Theese 3 stage are given to 3 different people. At the moment each one of them do it's part individually with some input fixed and in the end we do a full compilation with all together.  I know that's a bad way and so I wanna improve it. I would like to use a Top down approach with the Incremental Compilation (partitions). I've read what quartus handbook tells and so I think that the way to proceed is: 1- define the pinout of the device 2- define how the 3 block interconnect among them and to external pin 3- think about the clocks (which clock each block need, PLL, clock region, etc)  4- allocate the resources to a single design partition with some margin of course 5- compile the project telling that each region is empty and export the constraint for each region 6- give to each one of the 3 people that work to the design their constraints (I've understood that there is a sort of file that will be created that open a new project with all the information they need). 7- each developer open its project (using the file I spoke in point 7), develop its part, and give back a netlist that I've to import in the "master" project. 8- when I've all the 3 netlist I can compile the master project to have the final file.   Have I misunderstood or missed something? This approach shall be good also because if someone of the 3 developers has to change something, I've the new netlist to import in the master design and Quartus shall take less time to compile the project (atm we're over 1h.. on a EPS2S60 device)  I have also some question about what shall be leaved out of the partitions. I mean I spoke about clock management, is it good to leave PLL and global clock in the top level of the project?   Keep in mind that it's the first time for me that I work with Incremental Compilation and top down approach.. Until some years ago all the project was in charge to only one people but the CPU was external to FPGA and a lot of feature were not necesary.  Thx in advice for all the help you could give to me.

[Altera_Forum]

As expected the clk management will return to be the most critical part. 

As example in the "flat mode" I've an output of a PLL that is a regional clock, but now after the partition division it tell me that cannot fit that in a regional clock. It seems strange to me, but maybe is because I've keep the PLL in the "Top".  Moreover I've another problem about that resources: PLL! I mean in my design I've a clk that generate 2 clk output that go to 2 different partition (one is a clock in the block control and another is the clk for the Nios section). I cannot use another clock because theese 2 part MUST start always and this clock is the only one that is up when I turn on the board.  I know also that is bad to devide the clk input pin into 2 different PLL (that I can easily set in each partition), so what can I do?  And more in general how do you use your PLL in a partitioned design?  As first I started with a Top Down approach that is simple to do some practice (I know for sure that it work in flat mode and all the problem I'll have will be derived by the partitioning approach).  I hope someone could help, I can't believe that I'm the only one that wanna use this approach.