How to suppress optimization in Quartus

[Altera_Forum]

I'm trying to implement asynchronous cells on Altera Cyclone 2. The primitive cells are functionnal when I map it alone one the board. But when I use it in more complexe design, the tool makes some optimiztions and so my design doesn't work. I need to suppress all the optimizations concerning the mapping, but I don't know where. Any help is welcome!

[Altera_Forum]

I might be forgetting something, but I think anything described with WYSIWYG primitives will be retained if Analysis & Synthesis netlist optimizations and physical synthesis in the Fitter are turned off project wide in the Settings dialog box or disabled for that part of the design by setting "Netlist Optimizations" to "Never Allow" in the Assignment Editor. 

 You can use WYSIWYG primitives to describe the exact logic in each LUT and the configuration of each register. You can't control which inputs to a LUT are used, but if you get a result you like you can use incremental compilation to preserve placement and routing. That should keep the LUT inputs from changing.  See the "Designing With Low-Level Primitives User Guide" available under "Design Guidelines and Applications" at http://www.altera.com/literature/lit-qts.jsp. From the user guide:    --- Quote Start ---  Using low-level primitives in your design enables you to control the hardware implementation for a cone of logic in your design. These cones can be as small as an LCELL instantiation, which prevents the Quartus II synthesis engine from performing optimizations, to larger, more complex examples that specify the encoding method for a finite state machine (FSM).  --- Quote End ---    Even though you are using Cyclone II, you might be interested the examples in the "Advanced Synthesis Cookbook: A Design Guide for Stratix II, Stratix III, and Stratix IV Devices". The link for the cookbook is just above the link for the primitives user guide.