How to synthesize a CPU with a FSM behavioral module

Altera_Forum · ‎01-22-2011

Hi all,

I'm new in Verilog and FPGA design.

I write a code to implement simple ALU and Memories to do simple STORE and ADD operation.

After compilation, the tool reports that Clock Hold not operational because

the clock Skew>Data Delay. And there are also some warnings that latches are inferred.

I am wondering is there something wrong with my code? For my CPU, there is only one general purpose register AC(accumulator). MA is the address register and MD is the data register. IA, IB are index registers, which are not used in this case.

In the state3 of my FSM,if it's indirect addressing mode, I think I am trying to write values to AC, MA and MD twice in one clock cycle. Will that cause problems?

If anyone can help, thanks a lot...


module CPU1(clk,reset,AC);
input clk,reset; 
output  AC;
reg  MEM;
reg CF;
reg  PC,MA,IA,IB;
reg  MD,AC,IR;
reg  state,nextstate;
parameter state0=2'b00,
          state1=2'b01,
          state2=2'b10,
          state3=2'b11,
          
          DIRECT=2'b00,
          INDIRECT=2'b01,
          INDEXED=2'b10,
          OTHER=2'b11,
          
          LOAD=3'b000,
          ADD=3'b001;
          
initial
begin
PC=0;
IR=0;
MEM=000_00_0000000000100; //Load M into AC
MEM=001_00_0000000000011; //Add M to AC
MEM=000_00_0000000000000; //DOES NOTHING
MEM=000000000000001100; //DATA
MEM=000000000000000010; //DATA
end
always@(*)
case(state)
state0:begin
         nextstate=state1;
         MA=PC;
         PC=PC+1;
       end
       
state1:begin
         nextstate=state2;
         MD=MEM;
       end
       
state2:begin
         nextstate=state3;
         IR=MD;
       end
state3:begin
         case(IR)
         LOAD:begin
                case(IR)
                DIRECT:begin 
                         MA=IR;
                         MD=MEM;
                         AC=MD;
                       end
                INDIRECT:begin
                           MA=IR;
                           MD=MEM;
                           AC=MD;
                           MA=AC;
                           MD=MEM;
                           AC=MD;
                         end
                INDEXED:;
                OTHER:;
                endcase
              end
                          
         ADD:begin
               case(IR)
               DIRECT:begin
                        MA=IR;
                        MD=MEM;
                        AC=AC+MD;
                      end
               INDIRECT:begin
                          MA=IR;
                          MD=MEM;
                          MA=MD;
                          MD=MEM;
                          AC=AC+MD;
                        end
               INDEXED:;
               OTHER:;
               endcase
             end
        
         default:begin
                   case(IR)
                   DIRECT:begin
                        MA=IR;
                        MD=MEM;
                        AC=AC+MD;
                      end
                   INDIRECT:begin
                          MA=IR;
                          MD=MEM;
                          MA=MD;
                          MD=MEM;
                          AC=AC+MD;
                        end
                   INDEXED:;
                   OTHER:;
                   endcase
                 end
         
         
         endcase
       end
       
default:begin
          nextstate<=state0;
        end
endcase
always@(posedge clk)
if(~reset)
state<=state0;
else
state<=nextstate;
endmodule

Altera_Forum · ‎01-22-2011

Do you have outputs?

As far as I know every digital module (in fact any system) is based on having inputs and outputs. The functionality decides outputs based on inputs and internal states. I know some may not have explicit input e.g. oscillators but still have input...

edit: only exception is testbench (simulator tools)

Altera_Forum · ‎01-22-2011

kaz,

I added the accumulator as the output. But I met another problem.

I could not find the values of M in simulation.

Are we able to download data to Memory on FPGA with verilog inital block as I did in this case?

Altera_Forum · ‎01-22-2011

What do you do to these M values? do they affect the output?

Compilers are designed (by software people) to remove any logic that does not affect the outputs because it is seen as useless waste of logic and will affect the reputation of their devices so be kind to them.

Altera_Forum · ‎01-22-2011

I believe your state3 does not move any further. Thus your FSM starts st state0 and moves to state3 and stops there. As a result M value stays zero.

Altera_Forum · ‎01-23-2011

kaz,

the synthesis tool reports clock hold not operational due to Clock Skew>Data Delay in the compilation report.

Do you know how to fix this:(

thanks.

Altera_Forum · ‎01-23-2011

clock skew is a repeated scenario for many beginners and has been addressed in several threads.

In FPGAs (as opposed to ASICs) the designer must use the clock network (dedicated clock pins and routing). As such the fitter takes care of tSU of all internal registers by restricting fmax and takes care of tH by making sure that clock arrives at latching register not delayed with respect to data.

If the designer opted for gating the clock then clock may be delayed more than data and the fitter cries in despair. So if you have to gate the clock make sure you put it back to rest on global routing. I don't normally gate my clocks at all. If I have to then I use altera's clock mux to bridge over. You can also use settings in quartus or HDL attributes to reconnect.