PLL issue

[Altera_Forum]

Hi 

 I am using cyclone II and quartus II v6.0. In my design I have selected base clock 100MHz and want to select SOPC Builder clock with the help of PLL 130MHz and 4MHz(required for black and white video and VGA port). But message appear on the top:    "PLL is unable to make factor of 4MHz".  (although the factors 1/25 is displayed in the GUI)   I cannot understand why this is so?   Can anyone suggest me something?   Thank You

[Altera_Forum]

The factors displayed in the GUI are not the real factors, considering the feasible VCO frequency range. If you consult the Cyclone II device´handbook, you'll realize, that 4 MHz output can't be achieved. Cylone II also doesn't support cascading of PLL dividers, so you have to use a clock divider in the application logic. Depending on the intended operation of the 4 MHz domain, you'll probably prefer a 4 MHz clock enable rather than a divided clock.

[Altera_Forum]

One issue raised here is why the tool does not realise that its product (A PLL in this case) will be then rejected at fitting. 

Same may happen with signaltap. You spend an hour time until fitter says sorry can't do it. If it is all one package of tools from same vendor then what is going on and why they pass their work to the field engineer. We should have means to demonstrate !!

[Altera_Forum]

--- Quote Start ---    you'll probably prefer a 4 MHz clock enable rather than a divided clock.  --- Quote End ---     I am not getting you at this point, please will you explain?

[Altera_Forum]

See Quartus Software Handbook, Section II design guidelines, chapter clocking schemes, divided clocks respectively synchronous clock enable.