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Beginner
1,693 Views

How to use IOWR and IORD functions

Hello,

 

I'm building simple custom component and actually trying to start it up but in eclipse any function work. Have you any ideas where the problem is ? I attached code and screens from eclipse. There's another file with collatz program which works fine and to that i am trying to make interface.

 

Here's code:

library ieee; 

 

use ieee.std_logic_1164.all;

 

entity interface_slave is

port(

clk :in std_logic;

reset :in std_logic;

s0_read :in std_logic;

s0_readdata :out std_logic_vector(7 downto 0);

s0_write :in std_logic;

s0_writedata :in std_logic_vector(7 downto 0);

s0_waitrequest :out std_logic;

result_export   :out std_logic_vector(7 downto 0)

);

end interface_slave;

 

architecture arch1 of interface_slave is

signal waitRequset   :std_logic;

signal s0_readdata_reg,data_out_tmp :std_logic_vector(7 downto 0);

signal data_in_tmp :std_logic_vector(7 downto 0);

signal go_tmp,tmp_ready :std_logic;

 

component collatz

port(

rst,clk,go :in std_logic;

data :in std_logic_vector(7 downto 0);

result :out std_logic_vector(7 downto 0);

ready :out std_logic

);

end component;

 

begin

 

s0_readdata <= s0_readdata_reg;

s0_waitrequest <= s0_read and waitRequset;

 

process(clk,reset)

begin

if(rising_edge(clk)) then

if(reset = '1') then

go_tmp <= '0';

elsif(s0_write = '1') then

data_in_tmp <= s0_writedata;

go_tmp <= '1';

end if;

end if;

end process;

 

 

 

process(clk,reset)

begin

if(rising_edge(clk)) then

result_export <= s0_readdata_reg;

if(reset = '1') then

s0_readdata_reg <= "00000000";

waitRequset <= '1';

result_export <= "00000000";

 

elsif(s0_read = '1') then

waitRequset <= '0';

if(tmp_ready = '1') then

s0_readdata_reg <= data_out_tmp;

end if;

elsif(s0_read = '0') then

waitRequset <= '1';

end if;

end if;

end process;

poreg_instance: collatz port map(

clk => clk,

rst => reset,

go => go_tmp,

data => data_in_tmp,

result => data_out_tmp,

ready => tmp_ready

);

 

end architecture;

 

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2 Replies
Highlighted
New Contributor II
36 Views

Hello,

Are you sure that you followed the design cycle correctly?

If you want to make a custom component, and you do not start from scratch, you need to know how design files are copied / duplicated whey you compile / instantiate your qsys design.

If not, the code you modify will not necessarily be the code Quartus compiles.

One thing you can do is follow the tutorials that are available to create custom components.

 

Other thing you can do is put some diagnostics code in your code, use only the write IOWR command in Nios and see where you get.

What you also can do is use Signaltap and see what is going on in your FPGA but this is a bit more complicated.

 

Best Regards,

johi.

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Highlighted
Valued Contributor II
36 Views

Is the custom component connected to the NIOS CPU in your design? If so, check the base address for the custom component. In Eclipse, make sure to enable the small C libraries in the BSP editor when creating the project.

 

You can use the IOR/IOW commands to write to your custom component via the NIOS-2 CPU address space and offset.

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