How to use SDRAM on de2-70 board?

[Altera_Forum]

Hi everyone. 

 I'm newbie about Quartus II & Nios II, and using Altera DE2-70 board. I have two questions about SDRAM on DE2-70.   1. I don't want to use neither the SOPC builder nor the NIOS 2 processor.  In other words, I don't want to use SDRAM controller, C++ software. I want to use only verilog code and read/write data from/to SDRAM address directily.  I need to know how to read/write 16 bits word from/to an address location of the SDRAM, lets say 0x000000. and, do I need to concern about the refreshing time, precharge, ... etc?   2. If I have to use the SOPC builder & the NIOS 2 processor for SDRAM controller to use read/write data from/to SDRAM address,  how can I know SDRAM address about data in/out, and how can I express c or c++ code about read/write data from/to SDRAM address?     please let me know the solution or send me very simple source about sdram data & address using NIOS II/e cpu, JTAG UART, SDRAM..    thank you very much in advance.

[Altera_Forum]

first of all. 

why not using SOPC? the reason I guess is to access SDRAM via NiosII is too slow. you wanna access SDRAM as fast as it can. is that right?  you can use SOPC builder and Avalon-MM "Master". you can use bast transfer via Avalon bus.  this is easy way and safety way.  otherwise, you need to write long long code in HDL. like this. ttp://cache.micron.com/protected/expiretime=1282712493;badurl=ahr0cdovl3d3dy5tawnyb24uy29tly80mdquahrtba==/fe03e95c6f6a764e10b3fbfff5a207f7/1/32/512mb_sdr.pdf reading and writing process is not difficult. but you need to write initial process and precharge process as well.  I have done this before( for SDRAM / DDRSDRAM) it took months.( I was newbie too)  now, I was studied I did not need to write this. SOPC is handy enough.  if you still wanna try it, the hell is waiting for you.   good luck.

[Altera_Forum]

--- Quote Start ---  first of all. why not using SOPC? the reason I guess is to access SDRAM via NiosII is too slow. you wanna access SDRAM as fast as it can. is that right?   you can use SOPC builder and Avalon-MM "Master". you can use bast transfer via Avalon bus.   this is easy way and safety way.   otherwise, you need to write long long code in HDL. like this. ttp://cache.micron.com/protected/expiretime=1282712493;badurl=ahr0cdovl3d3dy5tawnyb24uy29tly80mdquahrtba==/fe03e95c6f6a764e10b3fbfff5a207f7/1/32/512mb_sdr.pdf reading and writing process is not difficult. but you need to write initial process and precharge process as well.   I have done this before( for SDRAM / DDRSDRAM) it took months.( I was newbie too)   now, I was studied I did not need to write this. SOPC is handy enough.   if you still wanna try it, the hell is waiting for you.    good luck.  --- Quote End ---       Thanks for your apply. after of all, I need to use SOPC buillder..   "you can use SOPC builder and Avalon-MM "Master". you can use bast transfer via Avalon bus."   I don't understand above sentence... 1. what kinds of sopc component do i use? NIOS II/e cpu, sdram controller, jtag uart, and avalon MM?? I don't know about avalon ...   2. after using above sopc builder component, do i have to use eclipse software for using sdram? or use verilog code to write/read sdram.   3. if i must use software for sdram data inout, I want to write some data to address of sdram, and read data from address of sdram using Nios II Eclipse (c or c++). (ex. address : 0x0002000, data : 11111111 0x0002001, data : 11111110 ...) how can i write/read data to/from address using c or c++.   I try to find some SDRAM examples, there are not about real/write data, but about only LED, Switch.. How can I get some instruction or code about using SDRAM data/address?   Thanks for your kindness.

[Altera_Forum]

since I don't have much time. 

 just quick reply.  1. what kinds of SOPC component do I use? you can make any type of IP-core, even CPU as well(it's not easy of course) Master / Slave / Stream sink / Stream source.   2. After using above SOPC builder component, do I have to use Eclipse Software for using SDRAM? or use verilog code to write/read SDRAM. no, your IP-core is able to access Memory Space directry like NiosII. also you can share memory between NiosII and your own HDL.  3. If I must use software for SDRAM data inout, I want to write some data to address of sdram, and read data from address of sdram using Nios II Eclipse (c or c++).  you can write/read memory in C/C++.( convenient) you also can write / read memory via your own HDL.(fast)  all right, I'm doing my job now. and I think this topic is going down and I can't find this again. you can e-mail to me@akiron.com.  if i have time, I can teach you step by step.

[Altera_Forum]

you don't have to email to me. 

 I got e-mails from this forum. (I didn't know that:rolleyes:)  all right see you later.

[Altera_Forum]

all, right. 

 I have some questions for you.  Q1. do you know custom IP?  which means the IP-core which you make.  Q2. can you access your SDRAM  can you access your SDRAM some how?  which means your system is connected to the SDRAM already.  Q3. Do you know HDL?  have you ever coded HDL and access to your hardware.  OK, I wait your answer. and then I "may" teach you how SOPC builder works.  unfortunately, I can not reply for 12 hours at least.  see you.

[Altera_Forum]

--- Quote Start ---  all, right.   I have some questions for you.   Q1. do you know custom IP? which means the IP-core which you make.   Q2. can you access your SDRAM can you access your SDRAM some how? which means your system is connected to the SDRAM already.   Q3. Do you know HDL? have you ever coded HDL and access to your hardware.   OK, I wait your answer. and then I "may" teach you how SOPC builder works.   unfortunately, I can not reply for 12 hours at least.   see you.  --- Quote End ---       1. I can make simple sopc system using NIOS II/e cpu, led, switch in DE2-70  example, but I don't know how they connected and how they operate. (like Avalon MM, I don't know about that)   I can understand and follow this example. ftp://ftp.altera.com/up/pub/altera_material/qii_9.0/computer_organization/de2-70/tutorials/verilog/tut_de2-70_sdram_verilog.pdf    I can just add some simple sopc components and make top verilog code for pin input, output & sopc components connection.   2. DE2-70 board has two 32MB SDRAM, but I have never used that before.   3. I know verilog hdl code and I can follow simple SOPC & NIOS II example about DE2-70, but I cannot make verilog code for complicated system.   Thanks for your help!

[Altera_Forum]

all right 

 this is first step for you. http://www.akiron.com/fpga/customipinstruction.pdf :)

[Altera_Forum]

Dear teddy80, 

IIRC, in the MegaWizard, there's a "raw" SDRAM controller core that you can use if you do not wish to use the SOPC and the Avalon interface.

[Altera_Forum]

--- Quote Start ---  all right   this is first step for you. http://www.akiron.com/fpga/customipinstruction.pdf :)  --- Quote End ---     sorry for my late apply because of other work. I followed your instruction, and got some questions.   1. before I follow the chapter 5, do i have to fpga pin assignment & sof download?   2. in chapter 5, I don't understand customAddress variable. I can't find customAddress variable in verilog hdl source.

[Altera_Forum]

> 1. before I follow the chapter 5, do i have to fpga pin assignment & sof download? 

yes you do. but I think you already have assigned project with the development board. if you have one, you don't have to assign the pins. but yes,you need sof download.   > 2. in chapter 5, I don't understand customAddress variable. > I can't find customAddress variable in verilog hdl source. the customAddress means "base address" in SOPC builder.( see figure 14)  so you simply replace "0x00000000" into the address you got in SOPC builder.   all right, I will prepare next stage in next morning (morning for me). see you.

[Altera_Forum]

--- Quote Start ---  > 1. before I follow the chapter 5, do i have to fpga pin assignment & sof download? yes you do. but I think you already have assigned project with the development board. if you have one, you don't have to assign the pins. but yes,you need sof download.   > 2. in chapter 5, I don't understand customAddress variable. > I can't find customAddress variable in verilog hdl source. the customAddress means "base address" in SOPC builder.( see figure 14)   so you simply replace "0x00000000" into the address you got in SOPC builder.     all right, I will prepare next stage in next morning (morning for me). see you.  --- Quote End ---     thank you for your kindness. I followed your instruction, and I made sopc verilog source code like this.   ============================================================   module SampleIP(iKEY, iCLK_50, oLEDG, coe_out); input [0:0] iKEY; input iCLK_50; output [7:0] oLEDG; output [31:0] coe_out;   ex1_SampleIP u_ex1_SampleIP ( .clk_0 (iCLK_50), .coe_out_from_the_mysampleip_0 (coe_out_from_the_mysampleip_0), .out_port_from_the_led_pio (oLEDG), .reset_n (iKEY) );   ============================================================   Q> I have a pin map of development board as you said, and I make top-level entity code for connection fpga board & sopc module by using ex1_SampleIP_inst.v code. What is the purpose of using LED? And iCLK_50, iKEY, oLEDG are already assigned in pin map, but, I don't know where ".coe_out_from_the_mySampleIP_0" is connected.  Do I have to connect from coe_out to LED for checking coe_out by using LED out?

[Altera_Forum]

just quick reply. 

 > Do I have to connect from coe_out to LED for checking coe_out by using LED out? you don't have to connect to the LEDs, but if you connect to LEDs instead of "out_port_from_the_led_pio". you can control LED from NiosII.  if you send a value like 0x01 via NiosII ( refer to address from SOPC ) you can lite one of led on the board.  but you don't have to connect to the LEDs. just leave them and set a value to the address( of your IP-core ) and read it as I told you in the document.  you can read the value. which means your value is saved on the register of your own IP.  all right, I will write next document for your next step.

[Altera_Forum]

hi, there. 

 I wrote a document which describes how to access Avalon-Bus in HDL. http://www.akiron.com/fpga/customipmaster.pdf here you can see the document.  next step, I will tell you how to read/write memories with using burst transfer. next step is final step of your question.  have a nice day.

[Altera_Forum]

--- Quote Start ---  hi, there.   I wrote a document which describes how to access Avalon-Bus in HDL. http://www.akiron.com/fpga/customipmaster.pdf here you can see the document.   next step, I will tell you how to read/write memories with using burst transfer. next step is final step of your question.   have a nice day.  --- Quote End ---     Hi.   I followed your first instruction, and I have the result as you said. I am trying to do your second instruction, and I have some questions again..   1. Why do I have to use cpuclock, sdramclock?  Why are they separated from mainclock(50Mhz)? (I don't know the reason about 3 clocks) And I can't setup Timer, DLL, so I tried to study about that.   2. What's the difference with Avalon-Master and Avalon-Slave? (I don't know what's the Avalon).. and Why do I use Custom-IP Ram? Can I just use SDRAM or On-chip Memory for data in/out from ram address? For example, can I use only SDRAM address(0x00800000 in your second instruction) instead of Custom-IP & On-chip Memory address(0x00002000 & 0x00002010) in 11 page of second instruction?   Thanks for your very kind help.

[Altera_Forum]

> 1. Why do I have to use cpuclock, sdramclock?  

> Why are they separated from mainclock(50Mhz)? no you don't. you don't have to multiple clocks. the reason why SOPC builder could have multiple clock is... cpu needs stable clock. sdram needs first clock and shifted clock. but you don't have to care about that. unless it gets problem. you just use the clock which examples prepared.   > 2. What's the difference with Avalon-Master and Avalon-Slave? > (I don't know what's the Avalon).. Avalon is a name. muster requests read and write like NiosII does. slave answer the requests of master.  > and Why do I use Custom-IP Ram? it means first document? this is a step one. when you finish the document. you know what Custom-IP is, don't you? this is a practice.   > Can I just use SDRAM or On-chip Memory for data in/out from ram address? > For example, can I use only SDRAM address(0x00800000 in your second instruction) instead of Custom-IP & On-chip Memory address(0x00002000  & 0x00002010) in 11 page of second instruction? hum. indeed. you can access to the SDRAM exactly same way, instead of on-chip RAM. but your SDRAM might have your NiosII program. I don't know which address is safe( you have to find way by your self).  you need to mind that this is a practice. I'm teaching foundation of customIP such as Avalon-MM Master / Avalon-MM Slave. after that, you have to lean how to attach the idea on your system by yourself.( <- cases are always different )  anyway, I will write last document. but I'm not sure if I can finish that by this weekend. see you later by then.

[Altera_Forum]

teddy80. 

 I need one or two days to finish the next document. sorry.

[Altera_Forum]

hi teddy80 

 actually I'm getting busy. and I could not write next document on this week. please refer to the document "Avalon-MM Memory mapped interface  http://www.altera.com/literature/manual/mnl_avalon_spec.pdf on page 23 it describes how burst transfer works.  sorry.

[Altera_Forum]

From where can I get information how to set up sdram controller?

[Altera_Forum]

Hi everyone, 

 I would like to ask any idea how to transfer data from verilog to NiosII for processing and transfer back to verilog again? Recently, I work on video processing project, the data is from the TV decoder (after converting to RGB/gray scale), required to transfer it to NiosII for processing. After processing is finished, the data is again transferred back to verilog for VGA display. Anyone can show me some simple example design how to transfer data to NiosII and transfer back to verilog by using avalon bus? Thanks a lot and I will appreciate it.   Best regard, TWK

[Altera_Forum]

Hello teddy, 

 Were you able to get Altera's SDRAM controller IP to work without NIOSII for your project? I've been trying to get it to work for a while without any luck.