Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Valued Contributor III
3,285 Views

How to use a module or interface instance in an interface?

Hello,every one! 

I have some problem in using interface of SystemVerilog: 

I have a predefined module and interface, and I want to use them in another interface. The example code of module in interface is: 

module predef_mod( input clk, input rst, output reg cntr_o ); always_ff @(posedge clk) if (rst) cntr_o <= 4'd0; else cntr_o <= cntr_o + 4'd1; endmodule interface use_predef_mod_if( input clk, input rst, output wire cntr ); predef_mod modi( .clk(clk), .rst(rst), .cntr_o(cntr) ); endinterface  

The example code of interface in interface is: 

interface predef_if( input clk, input rst, output reg cntr_o ); always_ff @(posedge clk) if (rst) cntr_o <= 4'd0; else cntr_o <= cntr_o + 4'd1; endinterface interface use_predef_intf_if( input clk, input rst, output wire cntr ); predef_if ifi( .clk(clk), .rst(rst), .cntr_o(cntr) ); endinterface  

The synthesizing result about the first code in QuartusII is reporting an error message like 'instantiation of module in interface is not allowed'. 

The result about the second code is raising an assertion failure in quartus_map.exe. 

I have read the interface section of SystemVerilog standard document:IEEE.1800-2012, and it seems that the standard had never announced that the usage like above is illegal. 

Maybe there are some syntax error? Please help me, Thanks! 

BTW: 

I have to say sorry for the possible typos in the code, For I'm typing these example code immediately on the forum, and I have no time to test them....
0 Kudos
11 Replies
Highlighted
Valued Contributor III
201 Views

You should never put a module inside an interface - it doesnt make sense. 

Modules are like chips on a board, and interfaces the interconnect between them.  

 

Why are you trying to instantiate a module inside an interface?
0 Kudos
Highlighted
Valued Contributor III
201 Views

Hi, Mr.Tricky: 

Thanks for your replying. 

There are some same processes in different interfaces in my design, and I wish to purge the duplicated code in these interfaces, so, I encapsulates these same process into a module and instantiate it in these interfaces. I think this would be helpful to maintain my design codes. 

 

On the other hand, if the module could not be intantiated in interface for it is recognized as a chip, why neither interface? Just as you said, the interface is like a group of interconnections, why couldn't it contain a group of another interconnections?
0 Kudos
Highlighted
Valued Contributor III
201 Views

You dont need to use interfaces at all. Modules contain other modules or interfaces. Interfaces just define a behaviour of a bus, and in real designs you dont need to use them at all.  

If you have a behaviour that needs to go into an FPGA, use modules. And instantiate modules inside modules.Interfaces just complicate things.
0 Kudos
Highlighted
Valued Contributor III
201 Views

Well, I agree your point.  

 

But how about interface? why interface couldn't be instantiated in another interface? They are all interconnections, I think there is no reason to forbid an interface containing another.
0 Kudos
Highlighted
Valued Contributor III
201 Views

Remember that Quartus only allows a specific subset of the language, as it must map to a real design. 

Interfaces are usually self contained from a real point of view, and should not contain another interface. 

 

SV is a very broad language that mostly covers verification. Quartus only supports the following: 

http://quartushelp.altera.com/14.1/mergedprojects/hdl/vlog/vlog_list_sys_vlog.htm
0 Kudos
Highlighted
Valued Contributor III
201 Views

 

--- Quote Start ---  

Remember that Quartus only allows a specific subset of the language, as it must map to a real design. 

Interfaces are usually self contained from a real point of view, and should not contain another interface. 

 

SV is a very broad language that mostly covers verification. Quartus only supports the following: 

http://quartushelp.altera.com/14.1/mergedprojects/hdl/vlog/vlog_list_sys_vlog.htm 

--- Quote End ---  

 

 

Well,It is so pity that Quartus don't support some feature such as modports,modport expression, for they can provide a good way to hide some feature that we don't want module to access. It is very useful in developing between many developers. 

 

But, in the limitation provided by the page,I still not found that the interface instantiated within interface is not supported:( . Have I missed anything?
0 Kudos
Highlighted
Valued Contributor III
201 Views

altera will only support the majority of use cases - extreme and corner use cases wont be covered unless there is a good market justification (ie. without it you'll buy a few $mil of Xilinx instead of Altera). 

 

While an interface within an interface is legal SV, I cant really see it being of any use that would make anything easier. 

If you really want it supported - raise a mysupport request with Altera (Altera dont really monitor these forums). They will give you a much better explanation as to why it's illegal.
0 Kudos
Highlighted
Valued Contributor III
201 Views

Well, thanks for your patient replying. I think I know what to do now...

0 Kudos
Highlighted
Valued Contributor III
201 Views

I've noticed that no vendor of FPGAs implements all the features of Verilog/VHDL, at least for the newer versions. Why are features added to languages if the vendors decide not to implement them? Should these language definitions be scaled back to something that all FPGA vendors agree to implement? Are abstraction features from computer science really all that useful for hardware design?

0 Kudos
Highlighted
Valued Contributor III
201 Views

 

--- Quote Start ---  

I've noticed that no vendor of FPGAs implements all the features of Verilog/VHDL, at least for the newer versions. Why are features added to languages if the vendors decide not to implement them? Should these language definitions be scaled back to something that all FPGA vendors agree to implement? Are abstraction features from computer science really all that useful for hardware design? 

--- Quote End ---  

 

 

The features added are now usually for simulation. You'll find Modelsim and Cadence have v good SV and VHDL support. 

For FPGAs, there isnt a lot you cannot do with existing language features, so the vendors dont see the point in adding more.
0 Kudos
Highlighted
Valued Contributor III
201 Views

I agree. It makes much more sense for vendors to put resources to designing chips than implementing unneeded new features in Verilog and VHDL.

0 Kudos