I'm using the quartus prime standard edition v17.1 to program my terasic tr4 board.
Now I wanted to include the DDR3 SDRAM to my project. I create the component with the platform designer. To the avalon memory mapped slave I connected two masters.
The first master connection is to write/read data with matlab. This works fine.
But the second connection to write/read data on the board failed. For this connection I use the Avalon-MM Pipeline Bridge.
I tested the write/read waveform first as static input parameters. After this failed I write some vhdl code to test. It failed again or the ddr3 couldn't configure itself.
Do I have to take a look at the waveform at special points or is it the wrong interface to write/read data from the board?
If you are writing your own VHDL design to interact with DDR3 via Avalon MM bus then you need to issue command correctly as per Avalon MM protocol spec requirement.
You can refer to below link for Avalon MM spec
Alternately you can generate DDR3 example design from DDR3 IP. The example design will comes with default RTL traffic generator and checker where you can use to verify DDR3 write/read transaction.