How to write testbench for 18x18 multiplier

LPokr · ‎12-13-2018

I need to write testbench for 18x18 multiplier, which reads input from a text file (at least 10 numbers). Every input has to have at least 1 one and 1 zero in 4 most significant bits, and half of the tested numbers are negative. If the results are correct, must be tested in testbench file.

Code is simple:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
ENTITY signed_mult18 is
    PORT(  a      : IN SIGNED (17 DOWNTO 0);
           b      : IN SIGNED (17 DOWNTO 0);
           result : OUT SIGNED (35 DOWNTO 0));
END ENTITY;
 
ARCHITECTURE rtl OF signed_mult18 IS
 
BEGIN
 
	result <= a * b;
	
END rtl;

Thank you very much.

Vicky1 · ‎12-14-2018

hi,

Here in community, no one will provide complete code so user should come with their own code/logic & people in community may help to make it correct/better appropriate.

In this case, I would like to suggest you need to use the STD.textio package that defines routines for reading and writing to

a text file , refer the below old thread ,

https://forums.intel.com/s/question/0D50P00003yyR8zSAE/vhdl-textio-hread-problem

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards

Vikas Jathar

(This message was posted on behalf of Intel Corporation)

Abe · ‎12-17-2018

You can create a basic testbench usign the Quartus university VWF editor and then have it generate VHDL/Verilog bench. Then modify the bench accordingly to read / write from files using textio library.