Hunting down a stuck port?

Altera_Forum · ‎07-19-2013

Anybody have suggestions for why a port might be stuck?

I can see in the RTL viewer that Quartus has replaced my inputs with 0. However, I don't know why. Everything up to that block is fine in the RTL viewer. The block in question is included below.

The lookup table files exist and are non-zero. This block simulates just fine in both modes outside of Quartus (I don't really simulate Verilog in Quartus if I can help it). So, I'm really confused as to why suddenly Quartus thinks that theta is constant inside this block.

Right now I'm trying to peel out a testcase that shows it without having to compile the universe.

Thanks.

module my_sincos_lut(/*AUTOARG*/
    // Outputs
    sin_out, cos_out,
    // Inputs
    theta, gclk
    );
    output signed  sin_out;
    output signed  cos_out;
    input signed   theta;
    input                gclk;
    
    /*AUTOWIRE*/
    
    /*AUTOREG*/
    // Beginning of automatic regs (for this module's undeclared outputs)
    reg signed    cos_out;
    reg signed    sin_out;
    // End of automatics
    reg signed    sin_rom;
    reg signed    cos_rom;
    wire          theta_unsigned = theta;
 
    initial
      begin
          $readmemb("my_lut_sin.txt", sin_rom, 0, 8191);
          $readmemb("my_lut_cos.txt", cos_rom, 0, 8191);
      end
`ifndef MY_LUT_CLOCKED
    always @(theta_unsigned)
      begin
          sin_out <= sin_rom;
          cos_out <= cos_rom;
      end
`else
    always @(posedge gclk)
      begin
          sin_out <= sin_rom;
          cos_out <= cos_rom;
      end
`endif
     
endmodule // my_sincos_lut