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I enabled encrypted bit stream with a key and programmed encrypted POF file with ekp file on max10. The program is running well on FPGA. I can not full erase any more the FPGA..

G_Shekar
Novice
669 Views

I also can not any further program the FPGA. it always fails in Program/Configure. I can not also do Verify/Blank Check. 

 

I can ONLY erase CFM0 and UFM....it shows 100% successful on progress bar. But nothing happens on FPGA. My program continues to run..

 

What could be the issue..I am attaching the images..

 

Appreciate pointers..

0 Kudos
8 Replies
Vicky1
Employee
222 Views

Hi,

Have you enabled the JTAG secure mode in the pof file?

Refer the "3.3.2.2. Generating .pof using Convert Programming Files" from link below,

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_config.pdf

Which Quartus Edition(lite/std/pro) , version & Kit used

 

Thanks,

Vikas

G_Shekar
Novice
222 Views

Hi Vicky,

 

Yes, I had JTAG Secure mode enabled. I did that after I had quartus.ini file placed under project folder. I was able to enable option for JTAG secure mode, in Convert Programming Files.

I guess problem started just after enabling JTAG Secure mode.

 

I use Quartus 18.1 lite with a license file for enabling encrypted bit stream..I was able to program and reprogram until I enabled JTAG secure mode.

 

I cant follow steps related to instantiating internal JTAG.. to disable JTAG secure mode.

 

Its a custom design board...I have two boards stuck with this situation. I can not program/configure anymore..

 

Highly appreciate your help on this to resurrect these boards :)

 

Thank you

Guna

Vicky1
Employee
222 Views

Hi Guna,

Please try to perform the below steps,

  1. Auto Detect
  2. Please don`t add any file
  3. simply perform full Erase
  4. Then add another .pof file to program.

please let me know , how it works for you.

 

Regards,

Vikas

G_Shekar
Novice
222 Views

Hi Vikas, No, I tried this..it did not work.

vj123
Novice
222 Views

Hi Guna,

Try to power up the device/custom design board by holding the "CONF_DONE" to low.

Please refer the below link & perform the action once you fully understood,

https://fpgawiki.intel.com/uploads/5/5f/MAX10_JTAG_Secure_Unlock_UG.pdf

 

Thanks

G_Shekar
Novice
222 Views

Thank you Vj, I dont know how to follow this very well..

 

I also found this..https://fpgacloud.intel.com/devstore/platform/15.0.0/Standard/max10-jtag-secure-unlock/

 

Again, not sure how to get this going. Could you help out on this.

 

Thank you

Vicky1
Employee
222 Views

Hi,

Have you checked with "CONF_DONE" as suggested in previous post?

Any observation..

 

Regards,

Vikas

G_Shekar
Novice
222 Views

Hi Vj, Vicky,

 

Yes I tried today, it does not seems to work. Once conf_done pin is low when powered, FPGA is not running the loaded bit stream as expected.

I tried to erase the chip in this state, it does not erase..after removing the low also I tried it does not perform erase.

 

Any thing I m missing?

 

Thank you

 

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