I also can not any further program the FPGA. it always fails in Program/Configure. I can not also do Verify/Blank Check.
I can ONLY erase CFM0 and UFM....it shows 100% successful on progress bar. But nothing happens on FPGA. My program continues to run..
What could be the issue..I am attaching the images..
Have you enabled the JTAG secure mode in the pof file?
Refer the "184.108.40.206. Generating .pof using Convert Programming Files" from link below,
Which Quartus Edition(lite/std/pro) , version & Kit used
Yes, I had JTAG Secure mode enabled. I did that after I had quartus.ini file placed under project folder. I was able to enable option for JTAG secure mode, in Convert Programming Files.
I guess problem started just after enabling JTAG Secure mode.
I use Quartus 18.1 lite with a license file for enabling encrypted bit stream..I was able to program and reprogram until I enabled JTAG secure mode.
I cant follow steps related to instantiating internal JTAG.. to disable JTAG secure mode.
Its a custom design board...I have two boards stuck with this situation. I can not program/configure anymore..
Highly appreciate your help on this to resurrect these boards :)
Please try to perform the below steps,
- Auto Detect
- Please don`t add any file
- simply perform full Erase
- Then add another .pof file to program.
please let me know , how it works for you.
Try to power up the device/custom design board by holding the "CONF_DONE" to low.
Please refer the below link & perform the action once you fully understood,
Thank you Vj, I dont know how to follow this very well..
Again, not sure how to get this going. Could you help out on this.
Hi Vj, Vicky,
Yes I tried today, it does not seems to work. Once conf_done pin is low when powered, FPGA is not running the loaded bit stream as expected.
I tried to erase the chip in this state, it does not erase..after removing the low also I tried it does not perform erase.
Any thing I m missing?