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Altera_Forum
Honored Contributor I
719 Views

I have a few simplistic code confusions

First question: 

Say we have: 

 

a : STD_LOGIC_VECTOR(0 TO 4); 

b : STD_LOGIC_VECTOR(2 TO 6); 

 

b <= "10100"; 

a <= b;  

 

How do the bits get assigned to "a" here? 

Does it go like this: 

b ---------------- a 

bit2 -- goes to -- bit0 

bit3 -- goes to -- bit1 

bit4 -- goes to -- bit2 

bit5 -- goes to -- bit3 

bit6 -- goes to -- bit4 

 

 

Likewise: 

Say we have: 

 

a : STD_LOGIC_VECTOR(2 DOWNTO 0); 

b : STD_LOGIC_VECTOR(2 TO 9); 

 

b <= "10100110"; 

a(2 DOWNTO 1) <= b(5 TO 6);  

 

How do the bits get assigned to "a" here? 

Does it go like this: 

b ---------------- a 

bit5 -- goes to -- bit2 

bit6 -- goes to -- bit1 

 

 

 

 

 

Second question: 

When I'm looking at something like this, this is a logic gate/construct right?  

 

b <= NOT(v) OR w OR (NOT(x) AND NOT(y) AND NOT(z)); 

 

I would just look at this in the same way as a logic diagram right? If NOTv is high OR w is high OR NOTx AND NOTy AND NOTz is high (all three), then b will be given a high?
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Altera_Forum
Honored Contributor I
31 Views

1. Correct. The position always matches based assigning 'left <= 'left and so on. 

2. Yes, this is a logic construct. But be aware the synthesis tool will do logic reduction to remove unnecessary logic and may merge cells if they have the same function, etc. So any diagrams may not be identical to your code, but should be functionally identical.
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