Cannot access $ieee in modelsim.ini

[Altera_Forum]

Hi, 

 We are certain that we had good Quartus and modelsim installation, and inside modelsim.in:  [Library] std = $MODEL_TECH/../std ieee = $MODEL_TECH/../ieee verilog = $MODEL_TECH/../verilog vital2000 = $MODEL_TECH/../vital2000 std_developerskit = $MODEL_TECH/../std_developerskit synopsys = $MODEL_TECH/../synopsys modelsim_lib = $MODEL_TECH/../modelsim_lib sv_std = $MODEL_TECH/../sv_std  although the above variables are defined, they cannot be printed with "set"   set ieee# can't read "ieee": no such variable      only the following variables, which are listed in to "ModelSim® User's Manual, v10.5b", are accessible, but many are not defined in modelsim.ini   Simulator Control Variables As with GUI Mode and Command Line Mode, simulator control for Batch Mode simulation is governed by which modelsim.ini variables are enabled and each variable’s setting.   AccessObjDebug IgnoreSVAError StdArithNoWarnings BreakOnAssertion IgnoreSVAFatal UserTimeUnit CheckpointCompressMode IgnoreSVAInfo PrintSimStats ClassDebug IgnoreSVAWarning WildcardFilter DefaultForceKind IgnoreWarning WLFCompress DefaultRadix IterationLimit WLFFilename DelayFileOpen NoQuitOnFinish WLFMCL ForceSigNextIter NumericStdNoWarnings WLFOptimize GCThreshold OnBreakDefaultAction WLFSizeLimit      Is this behaviro (not all modelsim.in variables accessible, whereas other variables not defined within modelsim.ini are accessible) by design?   greg

[Altera_Forum]

Hi, 

 Have you used  SYNTAX:set ieee= directory? Can you attach the transcript?  Let me know if this has helped resolve the issue you are facing or if you need any further assistance.  Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)

[Altera_Forum]

Hi, 

 The correct Tcl grammar would be "set ieee directory", without assignment symbol. The line inside the default installation generated modelsim.ini is "std = $MODEL_TECH/../std". Here is the full .ini:  ; Copyright 1991-2009 Mentor Graphics Corporation ; ; All Rights Reserved. ; ; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF ; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. ; std = $MODEL_TECH/../std ieee = $MODEL_TECH/../ieee verilog = $MODEL_TECH/../verilog vital2000 = $MODEL_TECH/../vital2000 std_developerskit = $MODEL_TECH/../std_developerskit synopsys = $MODEL_TECH/../synopsys modelsim_lib = $MODEL_TECH/../modelsim_lib sv_std = $MODEL_TECH/../sv_std ; Altera Primitive libraries ; ; VHDL Section ; altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf altera = $MODEL_TECH/../altera/vhdl/altera altera_lnsim = $MODEL_TECH/../altera/vhdl/altera_lnsim lpm = $MODEL_TECH/../altera/vhdl/220model 220model = $MODEL_TECH/../altera/vhdl/220model maxii = $MODEL_TECH/../altera/vhdl/maxii maxv = $MODEL_TECH/../altera/vhdl/maxv fiftyfivenm = $MODEL_TECH/../altera/vhdl/fiftyfivenm sgate = $MODEL_TECH/../altera/vhdl/sgate arriaii = $MODEL_TECH/../altera/vhdl/arriaii arriaii_hssi = $MODEL_TECH/../altera/vhdl/arriaii_hssi arriaii_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaii_pcie_hip arriaiigz = $MODEL_TECH/../altera/vhdl/arriaiigz arriaiigz_hssi = $MODEL_TECH/../altera/vhdl/arriaiigz_hssi arriaiigz_pcie_hip = $MODEL_TECH/../altera/vhdl/arriaiigz_pcie_hip stratixiv = $MODEL_TECH/../altera/vhdl/stratixiv stratixiv_hssi = $MODEL_TECH/../altera/vhdl/stratixiv_hssi stratixiv_pcie_hip = $MODEL_TECH/../altera/vhdl/stratixiv_pcie_hip cycloneiv = $MODEL_TECH/../altera/vhdl/cycloneiv cycloneiv_hssi = $MODEL_TECH/../altera/vhdl/cycloneiv_hssi cycloneiv_pcie_hip = $MODEL_TECH/../altera/vhdl/cycloneiv_pcie_hip cycloneive = $MODEL_TECH/../altera/vhdl/cycloneive stratixv = $MODEL_TECH/../altera/vhdl/stratixv  uploaded file:http://s000.tinyupload.com/index.php?file_id=30816614244553470924  After launching modelsim, what is weird is that   >set ieee# can't read "ieee": no such variable      but we can assign and read back:   set ieee "C:/intelFPGA_lite/16.1/modelsim_ase/std"# C:/intelFPGA_lite/16.1/modelsim_ase/std set ieee# C:/intelFPGA_lite/16.1/modelsim_ase/std    So it seems that the line for ieee in modelsim.ini was ignored. Should that be?   greg

[Altera_Forum]

Hi, 

 Yes, you are correct we are not able to read directly by using set IEEE. But we can see simulation libraries are loaded/read automatically by vsim with help of environment variable( MODEL_TECH).  example: # vsim -c top # Loading .../modeltech/sunos5/../std.standard # Loading work.top(a) # Loading work.for_model(a) # Loading ./for_model.sl # myentry = $MODEL_TECH/xyz # myentry = .../modeltech/sunos5/xyz # std = $MODEL_TECH/../std  Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)