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Altera_Forum
Honored Contributor I
789 Views

force_type confusion

Hi, 

 

For the “force” command there are three major types: deposit/drive/freeze. I got confused and could not find authoritative definition. Please confuse me if I am wrong: 

 

 

 

 

Difference 

Citation from modelsim_ref.pdf 

 

 

-deposit 

Can be overridden 

 

The <value> remains until the object is forced again, there is a subsequent driver transaction 

 

 

 

-freeze 

Cannot be overridden 

Freezes the object at the specified <value> until it is forced again or until it is 

unforced with the noforce command. 

 

 

-drive 

Allow contention, such that the command sets value to 1, and another drive drives it to 0, at some instant, then the value is X. 

attaches a driver to the object and drives the specified <value> until the object is 

forced again or until it is unforced with the noforce command. 

 

 

 

 

The ref also says “If the -freeze, -drive, or -deposit options are not used, then -freeze is the default for unresolved objects, and -drive is the default for resolved objects.” 

I am using the Quartus integrated modelsim and there are no value seem to be “undefined” or “unresolved”. What does “resolved” and “unresolved” mean here? 

 

 

 

Greg
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7 Replies
Altera_Forum
Honored Contributor I
66 Views

Resolved refers to resolved types in VHDL or 4 state logic in Verilog. 

In VHDL, resolved types are allowed multiple drivers. For example, if you have a signal declared as a std_logic, if you drive it with '1' and '0' from two difference sources, you get 'X'. (you'll get similar results for a reg or wire in verilog).  

It is illegal to have two drivers on a signal of an unresolved type (like an integer in VHDL).  

 

But the big question is why are you using the force command at all? Force is only really used to inject faults, and shouldnt be used to normally drive the design - this is what a testbench is for.
Altera_Forum
Honored Contributor I
66 Views

I did ponder on your answer carefully, but still have questions. 

 

Failure 1: 

In real circuits, different module/block execute in parallel. But in modelsim, as all were compiled and executes linearly according to a state machine, I doubt if “ambiguity/contention” can be simulated. 

For example in a contrived example: 

 

 

 

reg r1_reg; 

output r1; 

 

always @ (posedge clk) 

begin 

r1_reg<=1; 

end 

 

always @ (posedge clk) 

begin 

r1_reg<=0; 

end 

 

assign r1=r1_reg; 

 

 

 

as we run it, we always hit the first "always" before the second, so r1_reg forever is 0. Since HDL compiler always need to sort/give order to blocks before they can be arranged to execute, perhaps it is unavoidable and we could never easily simulate such racing/contention? 

 

 

Failure 2: 

wire, tri, wand,wor,buf,not: grammars of all these gates in Verilog are limited to strict logical expressions (+, &&, ^ operators, etc. Could you give counterexample?), and we failed to construct ambiguous drivers with this. 

 

Failure 3: 

 

 

input a0,a1;  

output a2; 

assign a2=a0;  

assign a2=a1; 

Quartus compiler fail and gives “a2 already assigned to a0” remark. 

 

 

 

 

 

Could you give nontrivial example to contrive multiple driver ambiguity in Verilog, and give remarks to the 3 failure above? 

 

 

greg
Altera_Forum
Honored Contributor I
66 Views

Always blocks all run in parrellel. This is not a programming language, but a hardware description language. Think of always blocks as infinite loops that get called whenever the condition after the @ is triggered. All always block run and function in parrallel. Think of them as two parrallel circuits.  

 

1. Both always blocks are diving r1_reg. Imagine 2 circuits each connected to the same wire. One drives 0, the other drives 1. Which one wins? you dont know, so the result is X, because reg is a 4 state type, and allows multiple drivers. If you had used blocking assignments, then a race condition will occur. The result WILL depend on compile order, and it likely will fail in synthesis. Moral of the story - dont use blocking assignments in always blocks. 

 

2. these are not gates, they are variable types. If you use system verilog, there are many more types. Stick to reg and wire, and you'll be less confused (or if it's SystemVerilog, just make everything the logic type, or integer). 

 

3. You have multiple drivers on a2. Its pretty clear as you're assigning a2 to two different things.
Altera_Forum
Honored Contributor I
66 Views

 

--- Quote Start ---  

Always blocks all run in parrellel. This is not a programming language, but a hardware description language. Think of always blocks as infinite loops that get called whenever the condition after the @ is triggered. All always block run and function in parrallel. Think of them as two parrallel circuits.  

 

1. Both always blocks are diving r1_reg. Imagine 2 circuits each connected to the same wire. One drives 0, the other drives 1. Which one wins? you dont know, so the result is X, because reg is a 4 state type, and allows multiple drivers. If you had used blocking assignments, then a race condition will occur. The result WILL depend on compile order, and it likely will fail in synthesis. Moral of the story - dont use blocking assignments in always blocks. 

 

2. these are not gates, they are variable types. If you use system verilog, there are many more types. Stick to reg and wire, and you'll be less confused (or if it's SystemVerilog, just make everything the logic type, or integer). 

 

3. You have multiple drivers on a2. Its pretty clear as you're assigning a2 to two different things. 

--- Quote End ---  

 

 

@1: 

"Always blocks all run in parrellel. Think of always blocks as infinite loops ..." 

Say an infinite loop is running, and upon posedge@clk, the programming language's event is generated, and the two always which were registered to the callback table would both get called. However, since we must assume there is a single thread running (almost 100% since modelsim runs on 1-core machine), there is always an order, or always an BL or JMP x86 jumping instruction executed first for one of the "always" before then for the other, so "clk" always get assigned twice at different host machine CPU cycle, it is not strict to say they run in "parallel". If the internal type definition for "clk" were to support contention and in this case were designed to produce "X", it requires such design which records each exact assignment time, and for each group of equivalent assignment instant time, do a value resolution. But just as in our example, we never got "X" but instead only the "later" assigned value. Sad! 

 

@2: 

I know they are not gates. I just cannot find way to connect multiple wires to them, for example effectively shorting two (or more) IO output together while making one of them std1 and another std0. I didn't find grammar to do that. 

 

For @1 and @2, could you show runnable verilog example which could produce "X" result in modelsim wave viewer? 

 

 

 

greg
Altera_Forum
Honored Contributor I
66 Views

1. This is just the way Verilog works, and the synthesis tool assumes each always is a separate peice of circuitry. VHDL on the other hand mandates that multiple processes driving the same signal cause multiple drivers, so similar code in VHDL will produce X: 

 

signal r : std_logic; process(clk) begin if rising_edge(clk) then r <= '1'; end if; end process; process(clk) if rising_edge(clk) then r <= '0'; end if; process;  

 

This will give you an X value on r. 

 

2. Not quite sure what exactly you're trying to do. In An FPGA, you cannot connect multiple signals together - the hardware doesnt allow it. The only place it is possible is the IO tristates, and it is only possible to drive an internal signal against an external one. You'll need to do multiple assigns to get the tri states working: 

 

assign io = (enable) ? a : 1'bz; 

 

assign a = (~enable) ? io : 1'bz; 

 

Of course, you would only use one of the above in the chip. The other would be in a testbench.
Altera_Forum
Honored Contributor I
66 Views

 

--- Quote Start ---  

 

 

2. Not quite sure what exactly you're trying to do. In An FPGA, you cannot connect multiple signals together - the hardware doesnt allow it. The only place it is possible is the IO tristates, and it is only possible to drive an internal signal against an external one. You'll need to do multiple assigns to get the tri states working: 

 

assign io = (enable) ? a : 1'bz; 

 

assign a = (~enable) ? io : 1'bz; 

 

Of course, you would only use one of the above in the chip. The other would be in a testbench. 

--- Quote End ---  

 

 

1. The chip (I am testing MAX V) can only be programmed from blaster and I never tested JTAG on that. Although JTAG is listed in handbook, the dev board has a J14 for JTAG, but the TDO and TMS are unconnected so JTAG cannot be used. As an off-topic question: does Stratix have JTAG debugging interface? And is it possible to read/write certain registers in runtime with that? Does doing that require huge amount of work because of the parallel/sync/timing issue of the circuit, comparing to JTAG debugging on off-the-shelf chips? If such per-register JTAG access were to be done, upon receiving each valid incoming JTAG signal the CPLD/FPGA would need to halt the entire chip (closing many paths/clocks, etc.) , require much complicated circuitry and that would also introduce significant delay / speed downgrade to the chip. I wonder if that had ever be implemented. 

 

2. "The other would be in a testbench". Do you mean the real "ee engineer's testbench (http://www.customtestbenches.com/images/electrical-test-bench-lg.jpg)" rather than the virtual HDL workbench? And that we manually connect a driven wire (with opposite value to the IO output) to the IO output, and use scope to test the contended "X" value? 

 

3. The "io" and "a" are related by "enable", but it didn't seem clear whether they are tristate or metastable. Could you explain in detail how they produce an contented "X"? 

 

 

 

--- Quote Start ---  

That's just how verilog designed... VHDL on the other hand... multiple drives 

--- Quote End ---  

 

4. I saw you and Pieter in another thread (http://pietervanderstar) all used VHDL example, and you referred to an limitation of verilog in this one. Does Altera or IC professionals consider verilog incomplete and amateurish, some how like C++ programmers viewing javascript? 

 

 

greg
Altera_Forum
Honored Contributor I
66 Views

1. I dont have any experience using JTAG other than as a programmer, so someone else will have to comment. 

2. Im refering to HDL testbench. 

3. The "enable" would be the tri-state enable input. This basically controls which way data is currently flowing. You cannot have two wires driving a bus. Putting the bus in a high impedance state (Z) allows data to be driven from another net. 

4. VHDL and Verilog both have advantages and disadvantages. There are many discussions on the internet. Although I think Verilog is generally more popular, but both can produce the same final circuits, and both can be powerful Verification environments. I still dont really understand what you're doing, or why you're trying to drive a net from 2 sources in verilog - you really wouldnt do this in a real circuit that you write in HDL. 

 

I think you are thinking too much like a software programmer and not a hardware designer.
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