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Hello
As written in title, I am trying to do RTL simulation using ModelSim and stuck with it. I'm a newbie to ModelSim and this question may seem stupid, but please help me (I looked for a lot of "How To"s but could not solve by myself). Below is the code below I am trying to simulate. It is just dividing the frequency.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FREQ_DIVIDER is
port(
CLK : in std_logic;
decountCLK : out std_logic
);
end entity FREQ_DIVIDER;
architecture BEHAVIOR of FREQ_DIVIDER is
-- Difining component(s)
-- Difining signal(s)
signal Q : std_logic_vector(25 downto 0);
-- Difining procedure(s)
begin
decountCLK <= Q(25);
process(CLK)
begin
if CLK'event and CLK = '1' then
if Q = 49999999 then Q <= (others => '0');
else Q <= Q + 1;
end if;
end if;
end process;
end architecture BEHAVIOR;
This code works fine I think (since I used this and other codes to blink LEDs and confirmed it worked as I imagined). And below is the test bench code for the above circuit.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FREQ_DIVIDER_TB is
end entity FREQ_DIVIDER_TB;
architecture BEHAVIOR of FREQ_DIVIDER_TB is
-- Difining components
component FREQ_DIVIDER
port(
CLK : in std_logic := '0';
decountCLK : out std_logic
);
end component FREQ_DIVIDER;
-- Difining signals
signal CLK : std_logic;
signal decountCLK : std_logic;
constant CLK_period : time := 20 ns;
begin
uut : FREQ_DIVIDER
port map(
CLK => CLK,
decountCLK => decountCLK
);
CLK_process : process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
end architecture BEHAVIOR;
I - compiled both of the file above on ModelSim, - did "Start Simulation", and - did "Run all." However when I see the waveform I get output signal (which is decountCLK) is always 'X'. CLK is working fine. Does anyone know how to solve this problem?? Any helps are appreciated.
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3 Replies
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The simulator does not know what you want for the initial value for Q. Supply an initial value for the signal, eg.,
-- Difining signal(s)
signal Q : std_logic_vector(25 downto 0) := (others => '0');
and it will work fine. An alternative method is to add a reset input and then add reset logic to the counter process. Cheers, Dave
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Dear Dave
--- Quote Start --- The simulator does not know what you want for the initial value for Q. Supply an initial value for the signal, eg.,
-- Difining signal(s)
signal Q : std_logic_vector(25 downto 0) := (others => '0');
and it will work fine. An alternative method is to add a reset input and then add reset logic to the counter process. Cheers, Dave --- Quote End --- I did the way you told me and it worked fine!! Thank you very much and I'm soooo happy now because this had been bothering me like 12 hours...
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You're welcome.
Cheers, Dave
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