I want to know the Type declaration and signal declaration.

Altera_Forum · ‎09-18-2014

i want to know the type and signal declaration why it is use and what is these mean in VHDL coding?

Thanks

Altera_Forum · ‎09-18-2014

It allows you to define new data types that allow you to write code that is easier to understand.

For example, lets say I am writing some DSP code using the VHDL data type "signed", but I have an array of signals, eg., the inputs to a parallel FFT, and I want to write a loop ... Since VHDL does not have an array of signed data type, I can define one ...


type signed_vector is array(natural range <>) of signed;
-- An Array of 8 16-bit signed values
signal fft_input  : signed_vector(0 to 7)(15 downto 0);
signal fft_output : signed_vector(0 to 7)(15 downto 0);
-- Some DSP logic ... perhaps involving loops, eg.,
for i in 0 to 7 loop
    fft_output(i) <= fft_input(i);
end loop;

Cheers,

Dave

Altera_Forum · ‎09-18-2014

super thx for explaining me :)

Altera_Forum · ‎09-18-2014

but i still confused about this part......

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.all;

USE IEEE.STD_LOGIC_ARITH.all;

USE IEEE.STD_LOGIC_UNSIGNED.all;

-- This code displays time in the DE2's LCD Display

-- Key2 resets time

ENTITY DE2_CLOCK IS

PORT(reset, clk_50Mhz : IN STD_LOGIC;

LCD_RS, LCD_E, LCD_ON, RESET_LED, SEC_LED : OUT STD_LOGIC;

LCD_RW : BUFFER STD_LOGIC;

DATA_BUS : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0));

END DE2_CLOCK;

ARCHITECTURE a OF DE2_CLOCK IS

TYPE STATE_TYPE IS (HOLD, FUNC_SET, DISPLAY_ON, MODE_SET, WRITE_CHAR1,

WRITE_CHAR2,WRITE_CHAR3,WRITE_CHAR4,WRITE_CHAR5,WRITE_CHAR6,WRITE_CHAR7,

WRITE_CHAR8, WRITE_CHAR9, WRITE_CHAR10, RETURN_HOME, TOGGLE_E, RESET1, RESET2,

RESET3, DISPLAY_OFF, DISPLAY_CLEAR);

SIGNAL state, next_command: STATE_TYPE;

SIGNAL DATA_BUS_VALUE: STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL CLK_COUNT_400HZ: STD_LOGIC_VECTOR(19 DOWNTO 0);

SIGNAL CLK_COUNT_10HZ: STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL BCD_SECD0,BCD_SECD1,BCD_MIND0,BCD_MIND1: STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL BCD_HRD0,BCD_HRD1,BCD_TSEC: STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL CLK_400HZ, CLK_10HZ : STD_LOGIC;

Altera_Forum · ‎09-18-2014

The new data type STATE_TYPE is created for a state machine. This allows you to write state machine code that transitions between states that have "meaningful" names, eg., rather than useless state names like S0, S1, S2, S3, etc, you can have WAIT_FOR_BUTTON, TURN_ON_LED, etc. When you synthesize the design to hardware, the synthesis tool can automatically decide how to encode the state registers (how many bits to use). When you simulate a state machine, the STATE_TYPE text is displayed in the simulator wave window (for Modelsim), so it makes it easier to debug your code.

Cheers,

Dave

Altera_Forum · ‎09-18-2014

super thanks again sir :)