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15461 Discussions

IBIS Model Creation for Agilex Discontinued?

dinom
Beginner
394 Views

I just found out through an IPS case that Quartus no longer supports creating IBIS models for user specific I/O standards and pinout for Agilex devices.  Why????   This is a huge disappointment and will make simulating things like DDR4 interfaces much more difficult and time consuming.  Now I must manually create the IBIS model by assigning models to each of my FPGA pins (hundreds of pins) by pulling in models from the generic Agilex IBIS file.  And if during simulation, I need to modify drive strength or impedance, I will need to manual adjust each pin again.  

Intel's big FPGA competitors still support IBIS model generation for FPGA feature.  Having the FPGA tool generate IBIS models not only saves time and effort, but it also keeps FPGA I/O settings in synch with the CCA designer's expectations. 

I can't imagine this was removed due to a technical challenge, so wondering why remove it?

 

0 Kudos
5 Replies
Ash_R_Intel
Employee
370 Views

Hi Dino,

Thanks for your feedback. This concern has already been raised to the engineering team. We don't yet have any confirmation on when this feature will be supported back. Customers will be definitely notified if it is back.

Appreciate your patience.


Regards


Ash_R_Intel
Employee
354 Views

Hi Dino,

For the DDR type applications on Agilex, it is recommended to perform HSPICE simulations instead of IBIS. I came to know that there is a script available to support customers for that. Please raise an IPS case related to EMIF area in case you want to try out that script.


Regards


JohnMoore
Novice
344 Views

The truth is in order to simulate a DDR4 interface you would need to generate a custom IBIS model anyway. The project specific IBIS would have driver settings that the FPGA designer had chosen, and would lack the 'Model Selector' section that would let you choose from a list of drivers. And without that section, you also can't turn ODT on and off, so you can only simulate in the 'write' direction for data signals.

I have generated my own IBIS model for simulating a DDRx channel for years using a Perl script after realizing it was simply too difficult to build one by using a text editor and copying/pasting the various models. The inputs are a netlist from the schematic, the raw IBIS model for the FPGA family, and (very important) the RLC for the package. Intel provides the IBIS model on their site but requires you to request the package RLC using a support ticket. And no, the RLC on the download site will not work - it is a default (likely an average) for any pins that don't have RLC values, and you have to have pin-specific RLC in your IBIS model if order to do any serious simulations (gives impedance and flight time info). The RLC should match the length information for the package so your PCB designer can match lengths to the DRAMs.

I simply include a short list of drivers in the custom IBIS model that I am likely to want to 'audition' and leave the rest of the models out - in the past IBIS models grew to over 300MB which made them very slow to access by the simulator. And each type of signal (DQ, Clock, Address/Control) gets a list of valid drivers to choose from (DQ get POD drivers, etc) in the Model Selector section.

So the project IBIS was partly helpful, but still needed alot of work to make it useful for simulation - creating one from scratch is really the only way to have an IBIS model that is useful in simulations. Hope this is helpful.

dinom
Beginner
320 Views

Sorry, I have to disagree with you that in order to simulate DDR4 in the past, I had to create my model from scratch.  The tool supported including the model selectors for each I/O type and I simply had to modify the file slightly based on the wiki below to get it to work.  Also, there was a switch to include the pin specific RLC values, not just the package ones.  So not sure why you think it needed to be created custom.  I've been using this method successfully since the DDR2 days.

 

https://community.intel.com/t5/FPGA-Wiki/Generating-and-Modifying-IBIS-files-for-Arria-10-EMIF/ta-p/...

JohnMoore
Novice
313 Views

I agree the RLC per pin would be included if the option was selected (I didn't always get that from my FPGA design team). And from what I can tell, the Model Selector would include ODT vs driver for the DQ signals of a DDRx design. But I don't think the tool would allow you to specify a number of different driver models for each signal group (address/control, DQ, clock). At least the wiki post doesn't mention how you would provide a list of such drivers. I generally want to try out the 34 ohm vs 40 ohm driver, for instance, and slew rate selection is always something I am interested in if it is provided (The Stratix 10 did not offer slew rate control for SSTL12 drivers). 

So I build an IBIS model with a selection of driver options that I audition as soon as I have a routed PCB to work with. That lets me identify any stubs (in a discrete design) that need to be minimized. You could do that work up front and communicate constraints to the PCB team if your flow allows for that.

So I have Model Selector sections for all three groups of signals. Yes, the tool may not allow selecting a driver that is in the IBIS model and we've worked around that in the past.

I'm curious to know if you have looked at the Agilex IBIS model. I have a separate post on its unique rising/falling waveforms and the huge difference in its slew rate settings. You may have already tripped across the post - it's simply titled "Agilex IBIS Model".

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