IC delay between Global clock buffer to IOBUF causing timing violations

[Altera_Forum]

Hi  

 I am trying to fix timing violations on my design, IC delay between global clock buffer to IOBUF is causing a negative slack of -1.698. I have tried to instantiate regional clock buffers instead of global clock buffers then i am running in to data path delay since option "FAST_INPUT REGISTER ON" to data ports is getting ignored.    Any suggestions how to fix this.

[Altera_Forum]

--- Quote Start ---  Hi   I am trying to fix timing violations on my design, IC delay between global clock buffer to IOBUF is causing a negative slack of -1.698. I have tried to instantiate regional clock buffers instead of global clock buffers then i am running in to data path delay since option "FAST_INPUT REGISTER ON" to data ports is getting ignored.    Any suggestions how to fix this.  --- Quote End ---    Are you driving the clock off the chip? More information here would be helpful, such as the output of "report_timing" for this path.

[Altera_Forum]

--- Quote Start ---  Are you driving the clock off the chip? More information here would be helpful, such as the output of "report_timing" for this path.  --- Quote End ---    Using ALTLVDS mega function fixed this issue, thanks for your response though.