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15996 Discussions

IEEE 1735 encryption in Quartus

Honored Contributor II

I have been using the IEEE 1735 encryption tool in Quartus Pro 17.1 but I cannot seem to find the right way of using the --simulator option. I issue the following command: 


C:>C:/intelFPGA_pro/17.1/quartus/bin64/encrypt_1735.exe --language=vhdl --simulation=mentor test.vhd 

An invalid option was supplied to the --simulation argument. 


I have tried to format it in all sorts of ways e.g. caps, brackets, ==, etc. but cannot find any way in which the tool seems to think that the argument is valid. If someone knows what how to get this to work then please do also let me know how to give multiple arguments to this simulator argument. I would like to be able to limit the encryption to 2 specific simulators.  


I also just wanted to make sure but as far as I understand, as long as I don't add --quartus to the arguments then the code will not be synthesizable.
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I made a try and I've the same issue with 17.1pro (linux).

I was able to encrypt with the simulation switch under 18.1pro (linux):

encrypt_1735 --language=verilog --simulation=mentor,cadence test_counter.v

For what I see in the encrypted file, If you don't add the --quartus swith, the encyphered aes key for intel is not added and it will not allow the quartus synthesis.

If you only add simulation switch, it will only allow IP decryption on the requested simulators.


FYI, I'm not familiar with this exe (encrypt_1735), I'm using a dedicated script that handle file encryption and where I embed several EDA 1735 keys to generate my custom encrypted lib.