Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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IO Pin status when Power up the Device

Altera_Forum
Honored Contributor II
‎02-02-2011 08:40 AM
1,586 Views

I am using Altera Cyclone device & programmed via Quarts II 7.2 to generate square pulse on a IO pin. 

When i power up the FPGA , IO pin goes momemnty high (180ms). 

Is there any option in Quarts II 7.2 or any version so that status of IO pins are low when power up.
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Altera_Forum
Honored Contributor II
‎02-02-2011 09:44 AM
671 Views

The behaviour is due to FPGA hardware (weak pull-up resistors) and not depending on Quartus. If you think about it, you'll realize, that the configuaration can't have an effect on the device behaviour before it's loaded. You can either change the polarity of your logic signal, or place a pull-down resistor of 1k to override the weak pull-up.

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