IO SStandards in Cyclone IV

[Altera_Forum]

Hello, 

I wander what is the relationship between the VCCIO voltage and the IO standard which is actually configured.  Lets say i select 3.3V LVCMOS standard for and an input signal. As long as the VCCIO for that bank is 3.3V, everything is clear, the treshold value for this input would be defined somewhere at the middle...  But if the VCCIO is supplied from external connector and it may be any value between from 1.2V to 3.4V, but the configuration value for that input remains 3.3 LVCMOS? what would happen to that treshold value? Would it change with the VCCIO value and maintain the current VCCIO middle value for treshold or it would remain as for 3.3V standard?

[Altera_Forum]

The Setting in the compiler will select some settings in the IO buffer that will select the input threshold levels (LVCMOS vs LVTTL) and drive strength, etc. However if the VCCIO is not the expected level, all bets are off. 

 In practice, LVCMOS switching threshold should be ~VCCIO/2 and VOH should be ~VCCIO - 0.4v or so, but timing will be compromised too.  Pete

[Altera_Forum]

--- Quote Start ---  The Setting in the compiler will select some settings in the IO buffer that will select the input threshold levels (LVCMOS vs LVTTL) and drive strength, etc. However if the VCCIO is not the expected level, all bets are off.  --- Quote End ---   I presume, you are just guessing. Comparing Cyclone III configuration files compiled with different I/O standard settings, I see, that Quartus effectively has only two different settings for regular single ended inputs  - 2.5 to 3.3V, no difference betweel LVCMOS and LVTTL - 1.2 to 1.8V In addition, PCI clamp diodes are turned on by default for the 2.5 to 3.3 V range, as specified in the datasheet.  It's not clear to me, what's actually changed between both ranges. It would be interesting to check the real input buffer thresholds. My assumption is, that the input will be still operational with an about 1/2 VCCIO threshold for a "wrong" voltage setting, but possibly reduced performance.  On output, I/O standards are mainly used to select a set of output transistors from current strength settings.

[Altera_Forum]

The timing isn't big issue in this particular design, but size is an issue. I have large amount of IO signals which have to be connected to connector, while the logic level for external signals may vary from 1.2V to 3.3V, determined by VDDREF analog input which is sample of the external card IOVCC. 

 The initial drive for this question was a need to avoid many of 2-supply logic level translators. The FPGA is built to operate in the multi-volt supply environment, but the actual logic levels for each io-bamk should be known and assigned in Quartus. But in this case these logic levels are unknown, and re-loading the FPGA with few different bitstreams isn't an option.  So you telling that if i'll assign in Quartus the IO to 3.3 LVCMOS, the inputs treshold values arn't absolute value (3.3V/2) but it always would be approximately VCCIO/2 for the whole voltage range? Even if the VCCIO is as low as 1.2V? I guess that the 3.3 LVTTL assignment changing the treshold value to little bit lower than 50%?

[Altera_Forum]

As reported, LVTTL and LVCMOS assignment doesn't change anything to the input buffer, which can be seen from the identical configuration bitstream. For the VCCIO variation, I suggest to make a basic test. Take care of the configuration related IO banks that don't work with voltages below 2.5 V. 

 Perhaps, an Altera forum user has tried before?