I'm going over the Constraining Source Synchronous Interfaces training and running a very simple design to test myself.
I'm trying both center aligned and edge aligned data in the design(with separate clocks).
here is the SDC I wrote:
I have setup issue for the center aligned clock:
And hold issue for the edge aligned clock:
I'm sure I'm missing some crucial input I didn't add but I don't know what.
Can someone explain to me what are the delays that set the data requires, they don't make sense to me.
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It is better to not think of them as constraints at all.
Instead they describe a circuit outside of the FPGA and that circuit, coupled with the circuit inside the FPGA, creates a full setup and hold analysis.
set_output_delay -max 0 -clock clk_out [get_ports data_out]
set_output_delay -min 0 -clock clk_out [get_ports data_out]
Looking at output constraint example, let's break down its components:
1. set_output_delay -> There is a register being driven by an FPGA output
2. -clock clk_out -> This register is clocked by our clock clk_out
3. -max/-min 0.0 -> The external delay has a max of 0.0 and min of 0.0
4. [get_ports data_out] -> The register is driven by port data_out
Looking at the schematic format:
We can see a circuit described outside of the FPGA, with a register feeding another register. This is the standard path analysis done on every path inside the FPGA.
Hope that clarify.
Btw, which training material are you referring to?
Regards,
Richard Tan
HI RichardTanSY_Intel,
Sorry for the late response, I thought I posted it but it probably wasn't sent.
I mainly interested in the input delay, since I'm going to write the data into internal FIFO and use it internally, so I don't really care about the output delay.
The paths that failing for me are those:
